VHDL: how to avoid latches

[Rorsh14]

Hi, I'm trying to build an PWM generator, and I plan to have 2 input signals (1 bit each), where one would increment duty factor, and another one would decrement it.

So, I have two signals, pulse length and pause length, and their sum will always be 100.

Signal definitions:

	signal pulse_lasting : std_logic_vector(6 downto 0) := "0001010";  --10
	signal pause_lasting : std_logic_vector(6 downto 0) := "1011010";  --90
	signal next_pulse_lasting : std_logic_vector(6 downto 0) := "0001010";  --10
	signal next_pause_lasting : std_logic_vector(6 downto 0) := "1011010";  --90

Here is how that process looks like:

duty: process(PULSE_incr, PAUSE_incr)  //input signals
	begin
		if(PULSE_incr = '1') then
			next_pulse_lasting <= std_logic_vector(unsigned(next_pulse_lasting) + 2);
			next_pause_lasting <= std_logic_vector(unsigned(next_pause_lasting) - 2);
		elsif(PAUSE_incr = '1') then
			next_pulse_lasting <= std_logic_vector(unsigned(next_pulse_lasting) - 2);
			next_pause_lasting <= std_logic_vector(unsigned(next_pause_lasting) + 2);
		else
			null;
		end if;
	end process;

Also, at one point (at the end of PWM cycle), I have these lines:

pulse_lasting <= next_pulse_lasting;
pause_lasting <= next_pause_lasting;

What I get reported is that next_pause_lasting and next_pulse_lasting will be generated as latches because they are not in each of if/else branches, but I don't see how I could fix it.

 

[KlausST]

Hi,

I´m not an expert in this field. I assume:

It seems it tells you to use a "clocked" process instead of combinatorial logic.
This avoids latches and uses flip flops instead.

But I could be totally wrong in this.

Klaus

 

[Rorsh14]

Hi, and thank you for your quick reply!

When I insert Clock into sensitivity list, and create "clocked process" with

if(CLK'event and CLK = '1') then ...

Then those latches go away, but I would prefer not to have this. I plan to connect those two input signals to mechanical buttons on my board, so CLK will be very fast (much faster than I can click and release the button), and I'm afraid it will "read" a lot of presses instead of just one.

 

[TrickyDicky]

What I get reported is that next_pause_lasting and next_pulse_lasting will be generated as latches because they are not in each of if/else branches, but I don't see how I could fix it.

This is because you have "null" in the else branch. Because you're not using a clock, or signals that behave like a clock, the FPGA has to build a latch to match the behaviour you have requested in the code.
You are kind of treating PULSE_incr and PAUSE_incr as clocks, but you are not matching the template for a synchronous process. I also recommend you use a clock, and not some other signal as a clock.

So, make your process synchronous, and the latch warnings will go away.

duty: process(clk)  //input signals
begin
  if rising_edge(clk) then

    if(PULSE_incr = '1') then
      next_pulse_lasting <= std_logic_vector(unsigned(next_pulse_lasting) + 2);
      next_pause_lasting <= std_logic_vector(unsigned(next_pause_lasting) - 2);
    elsif(PAUSE_incr = '1') then
      next_pulse_lasting <= std_logic_vector(unsigned(next_pulse_lasting) - 2);
      next_pause_lasting <= std_logic_vector(unsigned(next_pause_lasting) + 2);
    
    end if;
    
  end if;
end process;

 

[KlausST]

Hi,

mechanical switches:
There is always the problem of bouncing contacts. You can avoid this with passive filters or programmed logic.

And you should make your key press logic rather edge triggered than level triggered.

Klaus

 

[ThisIsNotSam]

Hi, and thank you for your quick reply!

When I insert Clock into sensitivity list, and create "clocked process" with

if(CLK'event and CLK = '1') then ...

Then those latches go away, but I would prefer not to have this. I plan to connect those two input signals to mechanical buttons on my board, so CLK will be very fast (much faster than I can click and release the button), and I'm afraid it will "read" a lot of presses instead of just one.

you need clocked logic and some debouncing stages. latches are not the way to go here.

 

[TrickyDicky]

Hi, and thank you for your quick reply!

When I insert Clock into sensitivity list, and create "clocked process" with

if(CLK'event and CLK = '1') then ...

Then those latches go away, but I would prefer not to have this. I plan to connect those two input signals to mechanical buttons on my board, so CLK will be very fast (much faster than I can click and release the button), and I'm afraid it will "read" a lot of presses instead of just one.

You will need to "debounce" then inputs, then create an edge detector circuit, so you can detect when the button is pressed.
Latches are very undesirable, as they cannot be timed with the timing analysis tool. Using latches is a very bad habit so you should not use them