Rorsh14
Newbie level 4
Hi, I'm trying to build an PWM generator, and I plan to have 2 input signals (1 bit each), where one would increment duty factor, and another one would decrement it.
So, I have two signals, pulse length and pause length, and their sum will always be 100.
Signal definitions:
Here is how that process looks like:
Also, at one point (at the end of PWM cycle), I have these lines:
What I get reported is that next_pause_lasting and next_pulse_lasting will be generated as latches because they are not in each of if/else branches, but I don't see how I could fix it.
So, I have two signals, pulse length and pause length, and their sum will always be 100.
Signal definitions:
Code:
signal pulse_lasting : std_logic_vector(6 downto 0) := "0001010"; --10
signal pause_lasting : std_logic_vector(6 downto 0) := "1011010"; --90
signal next_pulse_lasting : std_logic_vector(6 downto 0) := "0001010"; --10
signal next_pause_lasting : std_logic_vector(6 downto 0) := "1011010"; --90
Here is how that process looks like:
Code:
duty: process(PULSE_incr, PAUSE_incr) //input signals
begin
if(PULSE_incr = '1') then
next_pulse_lasting <= std_logic_vector(unsigned(next_pulse_lasting) + 2);
next_pause_lasting <= std_logic_vector(unsigned(next_pause_lasting) - 2);
elsif(PAUSE_incr = '1') then
next_pulse_lasting <= std_logic_vector(unsigned(next_pulse_lasting) - 2);
next_pause_lasting <= std_logic_vector(unsigned(next_pause_lasting) + 2);
else
null;
end if;
end process;
Also, at one point (at the end of PWM cycle), I have these lines:
Code:
pulse_lasting <= next_pulse_lasting;
pause_lasting <= next_pause_lasting;
What I get reported is that next_pause_lasting and next_pulse_lasting will be generated as latches because they are not in each of if/else branches, but I don't see how I could fix it.