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Vhdl fpga implementation (subroutine call, assign port)

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Jan 25, 2014
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hi i have started learning vhdl. I am tryimg to display a string in FPGA spartan 3E. Please someone help me , because i cant understand how to call a subroutine in fpga . I mean if in the program some statements need to get executed many times then its quite impractical to write those statements in the program again & again. so i am trying to get something equivalent to GOTO in C , or call subroutine type used in microprocessors.
Besides i also want to know that say if 'A' is assigned as a output port as A:OUT STD _ LOGIC , then in the program can we write A<= 'p' in order to display P in lcd or we need to define another signal in the program. like , Signal c:std_ logic

and then in architecture C <= 'p'. If so then why ?? I mean why cant we write A<='p'.


You're approaching the problem all wrong. An FPGA is nothing like a processor - its a big block of hardware. You VHDL descibes a "chip" that gets placed inside the FPGA. each entity is it's own chip and each chip connects to other chips (like on a circuit board). So there is no such thing as a subrouting, because all hardware always exists and always runs in parrallel.

I suggest you take up a good VHDL tutorial, and find a good digital logic text book. Then when you come back to the problem, draw the circuit you intend to create before you write any VHDL. this is a Hardware Description Language. WIthout understand what hardware you want, theres no chance of writing any meaningful code.

ERROR:HDLParsers:164 - "C:/Users/user/Desktop/phd/xilinx/led/led2.vhd" Line 61. parse error, unexpected PROCEDURE
ERROR:HDLParsers:164 - "C:/Users/user/Desktop/phd/xilinx/led/led2.vhd" Line 73. parse error, unexpected PROCEDURE

-- Company: 
-- Engineer: 
-- Create Date:    00:44:57 05/11/2015 
-- Design Name: 
-- Module Name:    led2 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
-- Dependencies: 
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
library IEEE;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity d is
    Port ( clk : in  STD_LOGIC;
           d : in STD_LOGIC;
           q : out  STD_LOGIC);
end d;

architecture Behavioral of d is

 process ( clk ,d )
 if (clk <='1') then 

end if;
procedure add;..............  [B]line 61[/B]

end process; 


end Behavioral;

procedure add is ....... [B]line 73[/B]

variable a,o :integer := 1
o:= a+1;

end procedure;

plz correct me.i have mentioned the lines of errors.
Last edited by a moderator:

using the procedure keyword is declaring a new procedure, and you cannot declare a procedure inside the run time area of a procedure, it must be declared before the begin. If you intended to call this procedure, then you cannot call a procedure that has not been declared yet.

Procedures must be declared in the declarative region of something. ie. before the "begin"

Procedures can be used to avoid repetition within a process. For example, many FSMs have an idle state with a lot of logic. Often, states that transition to the idle state could also skip the idle state and move directly to an active state. Developers often transition to the idle state for 1 cycle just to make the code easier to read and avoid the repetition (and associated maintainence issues). With a procedure, you can avoid the repetition. The implementation is not much larger, but may be slower.

I suggest you avoid them for now as their proper use in synthesis relies on a firm understanding of logic design in VHDL. It does sound like you are still trying to directly target a CPU.

IMO, procedures are eventually worth looking at.

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