VHDL fatal error in Architecture behavioral

[hossam abdo]

what is the meaning of this error in vhdl
"Fatal error in Architecture behavioral at Get_Multiple_Block_Sec_Status.vhd line 50"


note : Get_Multiple_Block_Sec_Status is the name of the code design

 

[blooz]

re: question in vhdl

what is the meaning of this error in vhdl
"Fatal error in Architecture behavioral at Get_Multiple_Block_Sec_Status.vhd line 50"


note : Get_Multiple_Block_Sec_Status is the name of the code design

Please Post the code then it could be fixed

 

[hossam abdo]

Re: question in vhdl

the code


----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Get_Multiple_Block_sec_status is
Port ( MBSS_en, R_BSS_en : in STD_LOGIC;
MBSS_first_block_num : in STD_LOGIC_VECTOR (7 downto 0);
MBSS_num_of_blocks : in STD_LOGIC_VECTOR (7 downto 0);
MBSS_mem_data : in STD_LOGIC_VECTOR (31 downto 0);
MBSS_mem_addrs : out STD_LOGIC_VECTOR (4 downto 0);
MBSS : out STD_LOGIC_VECTOR(3 downto 0);
blocks_counter : out STD_LOGIC_VECTOR(2 downto 0);
MBSS_error : out STD_LOGIC_VECTOR (7 downto 0));
end Get_Multiple_Block_sec_status;

architecture Behavioral of Get_Multiple_Block_sec_status is
signal block0,block1,block2,block3 : integer;
begin
block0 <= conv_integer(STD_LOGIC_VECTOR(MBSS_first_block_num(4 downto 0)));
block1 <= block0 + 1;
block2 <= block0 + 2;
block3 <= block0 + 3;
MBSS_mem_addrs <= "11101"; -- addrs of the checker block

-- taking the values of the cjecking bits
MBSS <= MBSS_mem_data(block3)&MBSS_mem_data(block2)&MBSS_mem_data(block1)&MBSS_mem_data(block0);

-- counter which send the num of blocks to outing block
blocks_counter <= "001" when(R_BSS_en='1' and MBSS_num_of_blocks=x"00")else -- only one block
"010" when(MBSS_num_of_blocks=x"01")else -- 2 blocks
"011" when(MBSS_num_of_blocks=x"02")else -- 3 blocks
"100" when(MBSS_num_of_blocks=x"03")else -- 4 blocks
"000";

--======================== error detection===========================
MBSS_error <=
x"0F" when (MBSS_en='1' and MBSS_num_of_blocks>x"03")else
x"10" when (MBSS_first_block_num>x"1B" and (R_BSS_en='1' or(MBSS_en='1' and MBSS_num_of_blocks>x"00")))
or(MBSS_first_block_num>x"1A" and MBSS_en='1' and MBSS_num_of_blocks>x"01")
or(MBSS_first_block_num>x"19" and MBSS_en='1' and MBSS_num_of_blocks>x"02")
or(MBSS_first_block_num>x"18" and MBSS_en='1' and MBSS_num_of_blocks>x"03")else
x"00";

end Behavioral;

 

[blooz]

The Uninitialized integer was the problem

here is the code with slight change ,simulation proceeds without any problems

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:33:14 04/21/2011 
-- Design Name: 
-- Module Name:    ert - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
			 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Get_Multiple_Block_sec_status is
Port ( MBSS_en, R_BSS_en : in STD_LOGIC;
[COLOR="blue"]MBSS_first_block_num : in STD_LOGIC_VECTOR (7 downto 0):="00000001";--initialized the number to 1 [/COLOR]
MBSS_num_of_blocks : in STD_LOGIC_VECTOR (7 downto 0);
MBSS_mem_data : in STD_LOGIC_VECTOR (31 downto 0);
MBSS_mem_addrs : out STD_LOGIC_VECTOR (4 downto 0);
MBSS : out STD_LOGIC_VECTOR(3 downto 0);
blocks_counter : out STD_LOGIC_VECTOR(2 downto 0);
MBSS_error : out STD_LOGIC_VECTOR (7 downto 0));
end Get_Multiple_Block_sec_status;

architecture Behavioral of Get_Multiple_Block_sec_status is
[COLOR="blue"]signal block0,block1,block2,block3 : integer:=1;[/COLOR]--here also initialized the integer to 1
begin
block0 <= conv_integer(STD_LOGIC_VECTOR(MBSS_first_block_num (4 downto 0)));
block1 <= block0 + 1;
block2 <= block0 + 2;
block3 <= block0 + 3;
MBSS_mem_addrs <= "11101"; -- addrs of the checker block

-- taking the values of the cjecking bits
MBSS <= MBSS_mem_data(block3)&MBSS_mem_data(block2)&MBSS_mem_data(block1)&MBSS_mem_data(block0);

-- counter which send the num of blocks to outing block
blocks_counter <= "001" when(R_BSS_en='1' and MBSS_num_of_blocks=x"00")else -- only one block
"010" when(MBSS_num_of_blocks=x"01")else -- 2 blocks
"011" when(MBSS_num_of_blocks=x"02")else -- 3 blocks
"100" when(MBSS_num_of_blocks=x"03")else -- 4 blocks
"000";

--======================== error detection===========================
MBSS_error <=
x"0F" when (MBSS_en='1' and MBSS_num_of_blocks>x"03")else
x"10" when (MBSS_first_block_num>x"1B" and (R_BSS_en='1' or(MBSS_en='1' and MBSS_num_of_blocks>x"00")))
or(MBSS_first_block_num>x"1A" and MBSS_en='1' and MBSS_num_of_blocks>x"01")
or(MBSS_first_block_num>x"19" and MBSS_en='1' and MBSS_num_of_blocks>x"02")
or(MBSS_first_block_num>x"18" and MBSS_en='1' and MBSS_num_of_blocks>x"03")else
x"00";

end Behavioral;

I have n't checked the correctness of the output .The Simulation works fine there is no fatal error .