VHDL entity 2D array question

[alexz]

vhdl entity array

I have defined a new type, which is a 2d array. An array of 10 latches 15 bits.

subtype	latchType	 is std_logic_vector(15 downto 0) ;
type 	latchesType  is array (9 downto 0) of latchType ;
signal	latches	:	latchesType := (others=>(others=>'0'));

Now, I want to instantiate an entity and pass a signal of this type to the entity.
How can I do this?

label: entity WORK myEntity(myARC) port map ( latches .... );


entity myEntity is
port
(latchesSignal : in latchesType ; ??????????

 

[aji_vlsi]

vhdl entity port array

I have defined a new type, which is a 2d array. An array of 10 latches 15 bits.

subtype	latchType	 is std_logic_vector(15 downto 0) ;
type 	latchesType  is array (9 downto 0) of latchType ;
signal	latches	:	latchesType := (others=>(others=>'0'));

Now, I want to instantiate an entity and pass a signal of this type to the entity.
How can I do this?

label: entity WORK myEntity(myARC) port map ( latches .... );


entity myEntity is
port
(latchesSignal : in latchesType ; ??????????

Yes, I don't see an issue in doing that. A good coding style is to puth your type in a package say "latch_pkg" and use it.

package latch_pkg;
subtype	latchType	 is std_logic_vector(15 downto 0) ;
type 	latchesType  is array (9 downto 0) of latchType ;
signal	latches	:	latchesType := (others=>(others=>'0'));
end package latch_pkg;

library work;
use work.latch_pkg.all;
entity myEntity is
port
 (latchesSignal : in latchesType  ; ??????????

label:   entity WORK myEntity(myARC) port map ( latches	.... );

Maybe I'm missing something?

HTH
Ajeetha, CVC
www.noveldv.com

 

[alexz]

array of vhd

You are definitely not missing anything!
Its just me, who has never used packages.
Where is the best place to define them?
Why do you include a signal in the package and how do you use it?
Is this signal becoming a global or something?


I have tried to copy your lines and get an error on the "subtype" line:
Error (10500): VHDL syntax error at intLatches.vhd(2) near text "subtype"; expecting "is"

 

[aji_vlsi]

vhdl array entity

You are definitely not missing anything!
Its just me, who has never used packages.
Where is the best place to define them?
Why do you include a signal in the package and how do you use it?
Is this signal becoming a global or something?


I have tried to copy your lines and get an error on the "subtype" line:
Error (10500): VHDL syntax error at intLatches.vhd(2) near text "subtype"; expecting "is"

The syntax was not 100% accurate, use Emacs for Template fixing, it will take care of those "is/begin/end" etc. Or quick google should get you the exact syntax.

Good Luck
Ajeetha, CVC
www.noveldv.com

 

[alexz]

vhdl array in entity

Right, it was actually the "is" was missing in the first line.

So, what about the signal defined in the package?

 

[aji_vlsi]

ncmirror array

Right, it was actually the "is" was missing in the first line.

So, what about the signal defined in the package?

Yes signal in package will become sort of global - wherever the packgae is used. See VHDL FAQ at www.vhdl.org/comp.lang.vhdl

BTW, AFAIK Signal in pkg is non synthesizable - if you care! What's the need for signals in package? For Testbench? Maybe you should use SignalSpy/NCMirror/HDL_XMR.


Ajeetha, CVC
www.noveldv.com