VHDL, CPLD code:Will this implementation works

[Bond_2007]

Hello,

I would like to use the following case statement:

test_bits<bit1,bit0>

case 00:
Make IO output PIN 7 high.
case 01:
Make IO output PIN 8 high.

If case 00 has ran, the IO PIN 7 is high, will it stays high even when case 01 is running? Is this a latch operation?

I am new to CPLD, any help is appreciated.

-B

 

[nand_gates]

Yes ur right! This will create a latch for both PIN7 and PIN 8
because you have not specified what value to drive on these pins
under all possible conditions!

 

[Bond_2007]

any other inputs are greatly appreciated.

-B

 

[vlsi_whiz]

As stated above, the code will result in two latches. To avoid latches use the following code structure:

test_bits<bit1,bit0>

case 00:
Make IO output PIN 7 high.
Make IO output PIN 8 low. 

case 01:
Make IO output PIN 8 high. 
Make IO output PIN 7 low.

You can also use the IF statement to do the same.