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VHDL, CPLD code:Will this implementation works

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Bond_2007

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Hello,

I would like to use the following case statement:

test_bits<bit1,bit0>

case 00:
Make IO output PIN 7 high.
case 01:
Make IO output PIN 8 high.

If case 00 has ran, the IO PIN 7 is high, will it stays high even when case 01 is running? Is this a latch operation?

I am new to CPLD, any help is appreciated.

-B
 

nand_gates

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Yes ur right! This will create a latch for both PIN7 and PIN 8
because you have not specified what value to drive on these pins
under all possible conditions!
 

Bond_2007

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any other inputs are greatly appreciated.

-B
 

vlsi_whiz

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As stated above, the code will result in two latches. To avoid latches use the following code structure:

Code:
test_bits<bit1,bit0>

case 00:
Make IO output PIN 7 high.
Make IO output PIN 8 low. 

case 01:
Make IO output PIN 8 high. 
Make IO output PIN 7 low.

You can also use the IF statement to do the same.
 

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