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VHDL: Converting a 2D array to 1D array

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rahulrs

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Thank you for looking at the post:

My design requires me to have an m*n array of records, which is stored in the td_array()().

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I need to compare records column by column. So I am building a column array (col_array) of records like this:

col_array(0) <= ( td_array(0)(0), td_array(1)(0), td_array(2)(0), td_array(3)(0) );
col_array(1) <= ( td_array(0)(1), td_array(1)(1), td_array(2)(1), td_array(3)(1) );
.
.
col_array(8) <= ( td_array(0)(8), td_array(1)(8), td_array(2)(8), td_array(3)(8) );


Is there a way to turn this into for-generate loop in VHDL to achieve this ?

I can have arbitrary 'm' and 'n' combinations.

Also do I have any better ways to do this ?

RRS
 
Last edited:

It depends on volume of data and processing needs for compare tolerances.

Your method is fine but in computer science there are other methods too such as working with vectors and pattern recognition using columns of data.

https://en.wikipedia.org/wiki/Array#In_computer_science
 

Thank you for your answer:
This is a synthesizable VHDL designs with m and n known at design time.
If I can re-frame my question:
I am just checking to see if there is VHDL syntax in a for-generate system where I can generate a column array out of a 2D array

RRS
 

You probably wouldnt want a for-generate loop. That is just for creating parrallel logic. All you are doing is creating a load of wire connections (no logic involved)
why not write a function to give you the array you want?


Code VHDL - [expand]
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function get_col( a : td_array_t; col : integer) return col_array_t is
  variable ret : col_array_t( a(col)'range );
begin
  for i in a(col)'range loop
    ret(i) := a(col)(i);
  end loop;
  
  return ret;
end function get_col;
 
col_array(0) <= get_col(td_array,0);

 
Thank You, this is an elegant solution. This works !!
 

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