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VHDL code synthesizeable or not, please help me

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mawais

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vhdl not code

Hi!
I am new to VHDL, I want to know that is the following piece of code synthesizeable or not

process (x)
begin
if(x' event and x = '0') then
.....
....
end if;
end process;

Where x is any signal or input other than the clock. I am perticularly refering to the event statement that is it possible to syntesize an edge trigreed process asynchronously in a real time hardware.
I am using Xilinx ISE 10.1. Can anyone tell how to know by using this software that which part or statement is not synthesizeable.
Thanks in advance.
best regards,
Muhammad Awais
 

kvingle

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Yes. You can do that.
Although not recommended, But it is synthesizable.

In ISE you can check synthesis report to check what is synthesized from you code.
Other way is to look at the RTL schematic after synthesis.
 

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