library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_a is
port (
clk : in std_logic;
rst_n : in std_logic;
q : out std_logic);
end counter_a;
architecture behave of counter_a is
signal count, count_nx : std_logic_vector(3 downto 0);
begin -- behave
q <= not (count(3) or count(2) or count(1) or count(0));
count_nx <= count + 1;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
count <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
count <= count_nx;
end if;
end process;
end behave;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_b is
port (
clk : in std_logic;
rst_n : in std_logic;
q : out std_logic);
end counter_b;
architecture behave of counter_b is
signal count, count_nx : std_logic_vector(3 downto 0);
begin -- behave
q <= not (count_nx(3) or count_nx(2) or count_nx(1) or count_nx(0));
count_nx <= count + 1;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
count <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
count <= count_nx;
end if;
end process;
end behave;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_c is
port (
clk : in std_logic;
rst_n : in std_logic;
q : out std_logic);
end counter_c;
architecture behave of counter_c is
signal count, count_nx : std_logic_vector(3 downto 0);
signal q_nx : std_logic;
begin -- behave
q_nx <= not (count(3) or count(2) or count(1) or count(0));
count_nx <= count + 1;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
count <= (others => '0');
q <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
count <= count_nx;
q <= q_nx;
end if;
end process;
end behave;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_d is
port (
clk : in std_logic;
rst_n : in std_logic;
q : out std_logic);
end counter_d;
architecture behave of counter_d is
signal count, count_nx : std_logic_vector(3 downto 0);
signal q_nx : std_logic;
begin -- behave
q_nx <= not (count_nx(3) or count_nx(2) or count_nx(1) or count_nx(0));
count_nx <= count + 1;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
count <= (others => '0');
q <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
count <= count_nx;
q <= q_nx;
end if;
end process;
end behave;