VHDL code of following structures?

[soc]

I would like to know the VHDL code for the hardware structure.

Thanks[/img]

 

[research235]

Hello Soc,

The VHDL code u have asked for is very easy and i am sure any VHDL programer will hardly take any time to code it .. But if this is turtorial one my advice is please to go through soem VHDL sides .. i am sure u can code urself in no time ,,,

One suggestion i can give is .. The first and second fig in the doc u have provided are interlinked .. u can write VHDL code for the first one and use this as component declaration for structural description of the second one ..

suresh

 

[soc]

Hello Soc,

The VHDL code u have asked for is very easy and i am sure any VHDL programer will hardly take any time to code it .. But if this is turtorial one my advice is please to go through soem VHDL sides .. i am sure u can code urself in no time ,,,

One suggestion i can give is .. The first and second fig in the doc u have provided are interlinked .. u can write VHDL code for the first one and use this as component declaration for structural description of the second one ..

suresh

Yes its easy for someone who know VHDL programming but for someone doing VHDL for the first time, such hardware structure is not easy to code.
It would be good if u can provide the code and then give the explanation how they are interlinked.

Thanks

 

[nand_gates]

Solution for 2.10...

library ieee;
use ieee.std_logic_1164.all;
entity FA is
  
  port (
    a    : in  std_logic;
    b    : in  std_logic;
    cin  : in  std_logic;
    cout : out std_logic;
    sum  : out std_logic);

end FA;
architecture behave of FA is
begin  -- behave
  sum <= a xor b xor cin;
  cout <= (a and b) or (b and cin) or (a and cin);    
end behave;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity serial_add16 is
  
  port (
    A     : in  std_logic;
    B     : in  std_logic;
    rst_n : in  std_logic;
    clk   : in  std_logic;
    sum   : out std_logic);

end serial_add16;

architecture behave of serial_add16 is
component FA
  port (
    a    : in  std_logic;
    b    : in  std_logic;
    cin  : in  std_logic;
    cout : out std_logic;
    sum  : out std_logic);
end component;
signal counter : std_logic_vector(3 downto 0);
signal zero : std_logic;
signal Cin, Cin_reg : std_logic;
signal Cout : std_logic;
begin  -- behave
  zero <= not (counter(3) or counter(2) or counter(1) or counter(0));
  with zero select
    Cin <= '0'  when '1',
           Cout when others; 
  registers: process (clk, rst_n)
  begin  -- process registers
    if rst_n = '0' then                 -- asynchronous reset (active low)
      counter <= (others => '0');
      Cin_reg <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      counter <= counter + 1;
      Cin_reg <= Cin;
    end if;
  end process registers;

  fa0 : FA port map (
    a    => A,
    b    => B,
    cin  => Cin_reg,
    cout => Cout,
    sum  => sum);
end behave;

 

[nand_gates]

Solutions for 2.14 a, b, c, d

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter_a is
  
  port (
    clk   : in  std_logic;
    rst_n : in  std_logic;
    q  : out std_logic);

end counter_a;

architecture behave of counter_a is
signal count, count_nx : std_logic_vector(3 downto 0);
begin  -- behave
  q <= not (count(3) or count(2) or  count(1) or count(0));
  count_nx <= count + 1;
  process (clk, rst_n)
  begin  -- process
    if rst_n = '0' then                 -- asynchronous reset (active low)
      count <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      count <= count_nx;
    end if;
  end process;

end behave;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter_b is
  
  port (
    clk   : in  std_logic;
    rst_n : in  std_logic;
    q  : out std_logic);

end counter_b;

architecture behave of counter_b is
signal count, count_nx : std_logic_vector(3 downto 0);
begin  -- behave
  q <= not (count_nx(3) or count_nx(2) or  count_nx(1) or count_nx(0));
  count_nx <= count + 1;
  process (clk, rst_n)
  begin  -- process
    if rst_n = '0' then                 -- asynchronous reset (active low)
      count <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      count <= count_nx;
    end if;
  end process;

end behave;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter_c is
  
  port (
    clk   : in  std_logic;
    rst_n : in  std_logic;
    q  : out std_logic);

end counter_c;

architecture behave of counter_c is
signal count, count_nx : std_logic_vector(3 downto 0);
signal q_nx : std_logic;
begin  -- behave
  q_nx <= not (count(3) or count(2) or  count(1) or count(0));
  count_nx <= count + 1;
  process (clk, rst_n)
  begin  -- process
    if rst_n = '0' then                 -- asynchronous reset (active low)
      count <= (others => '0');
      q <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      count <= count_nx;
      q <= q_nx;
    end if;
  end process;

end behave;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter_d is
  
  port (
    clk   : in  std_logic;
    rst_n : in  std_logic;
    q  : out std_logic);

end counter_d;

architecture behave of counter_d is
signal count, count_nx : std_logic_vector(3 downto 0);
signal q_nx : std_logic;
begin  -- behave
  q_nx <= not (count_nx(3) or count_nx(2) or  count_nx(1) or count_nx(0));
  count_nx <= count + 1;
  process (clk, rst_n)
  begin  -- process
    if rst_n = '0' then                 -- asynchronous reset (active low)
      count <= (others => '0');
      q <= '0'; 
    elsif clk'event and clk = '1' then  -- rising clock edge
      count <= count_nx;
      q <= q_nx;
    end if;
  end process;

end behave;

Added after 1 hours 3 minutes:

Solution for 2.12...

library ieee;
use ieee.std_logic_1164.all;
entity FA is
  
  port (
    a    : in  std_logic;
    b    : in  std_logic;
    cin  : in  std_logic;
    cout : out std_logic;
    sum  : out std_logic);

end FA;
architecture behave of FA is
begin  -- behave
  sum <= a xor b xor cin;
  cout <= (a and b) or (b and cin) or (a and cin);    
end behave;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity serial_mul16 is
  
  port (
    clk   : in  std_logic;
    rst_n : in  std_logic;
    a     : in  std_logic_vector(3 downto 0);
    bi    : in  std_logic;
    product : out  std_logic;
    i     : out std_logic_vector(3 downto 0));

end serial_mul16;

architecture structgen of serial_mul16 is
  component FA
    port (
          a    : in  std_logic;
          b    : in  std_logic;
          cin  : in  std_logic;
          cout : out std_logic;
          sum  : out std_logic);
  end component;
signal a_and_bi : std_logic_vector(3 downto 0);
signal cin_nx, cin : std_logic_vector(3 downto 0);
signal tmp_nx, tmp : std_logic_vector(4 downto 0);
signal count_nx, count : std_logic_vector(3 downto 0);
signal zero : std_logic;
begin  -- structgen
  count_nx <= count + 1;
  i <= count;
  zero <= not (count(3) or count(2) or count(1) or count(0));
  a_and_bi <= a and bi&bi&bi&bi;
  tmp_nx(3) <= '0';
  product <= tmp_nx(0);
  G_1: for I in 3 downto 0 generate
--                             A B cin cout sum 
    full_adder : FA port map
          (tmp(I+1), a_and_bi(I), cin(I), cin_nx(I), tmp_nx(I));
  end generate G_1;
counter: process (clk, rst_n)
begin  -- process counter
  if rst_n = '0' then                   -- asynchronous reset (active low)
    count <= (others => '0'); 
  elsif clk'event and clk = '1' then    -- rising clock edge
    count <= count_nx;
  end if;
end process counter;

registers: process (clk)
begin  -- process registers
  if clk'event and clk = '1' then    -- rising clock edge
    if zero = '1' then
      cin <= (others => '0'); 
      tmp <= (others => '0');
    else
      cin <= cin_nx;
      tmp <= tmp_nx;
    end if;
  end if;
end process registers;
    
end structgen;