VHDL Code Of 2 input XOR -gate

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channaveer_018

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Hi,
I am new to VHDL programing and i had written a VHDL code on 2 input XOR gate using process and it compiles successfully but in test bench waveform i am unable to get the output that is for all possible inputs i am getting 0 output , I am using Xilinx 9.1 and the following is code

entity XOR2 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end XOR2;

architecture Behavioral of XOR2 is
begin

process(A,B)
begin
if((A='0') and (B='1')) then
C<='1';
elsif((A='1') and (B='0')) then
C<='1';
else
C<='0';
end if;
end process;

end Behavioral;
 

There is no problem with the code ...
Works fine and here is the output in Xilinx ISE 13.1
 
Last edited:

Your code is fine.

Another way to have the XOR function is

Code VHDL - [expand]
1
2

if (A /= B) then C<='1';  -- if A not equal to B
else C<='0';

but in this case you will get a result of 1 even if the inputs are 'U' or 'Z'

or 

Code VHDL - [expand]
1

C<= (A XOR B );

which will give a result of 0/1 only is both inputs are set to 0/1

Alex
 
i guess the second solution is better because there is no need for process
 

You can use any of the three ways in or out of a process, you just have to change the if else that can be used only inside the process with when else that can be used out of a process.

Code VHDL - [expand]
1
2

C<='1' WHEN (A /= B)
ELSE  '0';


Code VHDL - [expand]
1
2

C<='1' WHEN ((A='0') and (B='1')) OR ((A='1') and (B='0'))
ELSE  '0';




Alex
 
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