vhdl code for state machine

[fanwel]

Hai,

Can anyone justify what the different between two line codes below:

1) case cycle is
when 0l1l7 =>cp<=SXT(bm,11)+b3;
end case

2) if cycle=2 or cycle=3 then
cm<=SXT(b2,11)-b3;
end if

I'm curious the function of "l". Is it it mean by "AND" function? Thanks in advance

 

[FvM]

At some point, it's reasonable to review a VHDL text book or language specification ...

It's a choices construct. when 0|1|7 => is true for the values 0, 1 or 7.

 

[fanwel]

At some point, it's reasonable to review a VHDL text book or language specification ...

It's a choices construct. when 0|1|7 => is true for the values 0, 1 or 7.

Hai FvM,

I have review a VHDL reference book, but I didn't find the type of line codes. Btw, from your statement above, its look like the line code is same meaning with "OR" gate. That means, it is same if I write like this:

if cycle=0 or cycle=1 or cycle=7 then
..............................

Is it I'm right? Thank in advance