I have written this VHDL code for serial transmission ................
entity serial_tx is
Port ( clk : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC);
end serial_tx;
architecture Behavioral of serial_tx is
signal clkout:std_logic:='0';
signal data:std_logic:='0';
signal count:integer:=0;
type state is(state1,state2,state3,state4,state5,state6,state7,state8,state9,state10);
signal current_state,next_state:state;
begin
process(clk)
begin
if clk'event and clk='1' then
count<=count + 1;
TxD <= data;
if count =4 then
clkout<= not clkout;
count<=0;
end if;
end if;
end process;
process(clkout)
begin
current_state<=next_state;
end process;
process(current_state,next_state)
begin
case current_state is
when state1=>
data <='0';
next_state<=state2;
when state2=>
data <='0';
next_state<=state3;
when state3=>
data <='1';
next_state<=state4;
when state4=>
data <='0';
next_state<=state5;
when state5=>
data <='0';
next_state<=state6;
when state6=>
data <='0';
next_state<=state7;
when state7=>
data <='0';
next_state<=state8;
when state8=>
data <='1';
next_state<=state9;
when state9=>
data <='0';
next_state<=state10;
when state10=>
data <='0';
next_state<=state1;
end case;
end process;
end Behavioral;
I m using '0' as start bit , '0' as stop bit and 8 data bits. I am transmitting each bit for 4 clock cycle. If this code is correct and will transmit some data on hyperterminal?
please reply.