vhdl code for serial communication

[j hemangini]

vhdl serial communication

According to written in datasheet Using a standard, straight-through 9-pin serial cable, then on pressing number key 0,1,2 & 3 hypertermina should show following diaplay .

-----------------------------------------------------------------------------------------------

The key features of the Spartan-3A Starter Kit board are:
• Xilinx 700K-gate XC3S700A Spartan-3A FPGA in the Pb-free 484-ball BGA package
(FGG484)
• 4 Mbit Xilinx Platform Flash configuration PROM
• 64 MByte (512 Mbit) of DDR2 SDRAM, 32Mx16 data interface
• 4 MByte (32 Mbit) of parallel NOR Flash
♦ FPGA configuration storage
♦ MicroBlaze code storage/shadowing
♦ x8 or x16 data interface after configuration
• Two 16 Mbit SPI serial Flash
♦ STMicroelectronics and Atmel DataFlash serial architectures
♦ FPGA configuration storage
- Supports single configuration bitstream or multiple MultiBoot configuration
bitstreams
♦ Nonvolatile data storage
Figure 1-6: Use HyperTerminal and a Standard Serial Cable to Connect to Board
UG330_c1_06_032207
----------------------------------------------------------------------------------------------
But i am not getting any display on hyperterminal. What should be the problem.
if anyone have answer then please tell me.

 

[saikat]

vhdl serial

check the baud rate of board and pc. they should match!

 

[j hemangini]

vhdl serial port

As shown in datasheet i set the baud rate 57600 ,and i have tried with all the baud rates but no communication is taking place.

Added after 1 minutes:

As shown in datasheet i set the baud rate 57600 ,and i have tried with all the baud rates but no communication is taking place.

 

[kvingle]

serial communication in vhdl

just to make sure ....have you downloaded any UART core inside the FPGA?

 

[j hemangini]

serial communication vhdl

I have not download any UART core. But one thing to say that when i connect VGA port of board with monitor of computer it starts showing as written in datasheet. Then is there any need to download any UART core.
One more thing is that when i connect kit with hyperterminal and leave it for 10-15min and then press reset key then hyperterminal show some garbage like-
PH0Î:
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Ó
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XLIÈxÀBÎ!«












































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˜ç…žÄ礆¤¤Å§„â„…‡†ä¦ Ål†¼Ä¯¦ì„Ž„½Å¾„Þkïéˆ^Ž

 

[kvingle]

hyperterminal vhdl

I referred to your board user guide..the preloaded design has 4 different bit streams..
make sure you are using the third bit stream ...i.e. go to multiboot option as given in manual and boot ASCII Terminal bitstream.

 

[j hemangini]

vhdl hyperterminal

I tried to make communication using third bitstream , but i am facing the same problem. No serial communication is taking place.

 

[j hemangini]

vhdl code for serial port

I have written this VHDL code for serial transmission ................


entity serial_tx is
Port ( clk : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC);
end serial_tx;

architecture Behavioral of serial_tx is
signal clkout:std_logic:='0';
signal data:std_logic:='0';
signal count:integer:=0;
type state is(state1,state2,state3,state4,state5,state6,state7,state8,state9,state10);
signal current_state,next_state:state;
begin
process(clk)
begin
if clk'event and clk='1' then
count<=count + 1;
TxD <= data;
if count =4 then
clkout<= not clkout;
count<=0;
end if;
end if;
end process;

process(clkout)
begin
current_state<=next_state;
end process;

process(current_state,next_state)
begin
case current_state is
when state1=>
data <='0';
next_state<=state2;
when state2=>
data <='0';
next_state<=state3;
when state3=>
data <='1';
next_state<=state4;
when state4=>
data <='0';
next_state<=state5;
when state5=>
data <='0';
next_state<=state6;
when state6=>
data <='0';
next_state<=state7;
when state7=>
data <='0';
next_state<=state8;
when state8=>
data <='1';
next_state<=state9;
when state9=>
data <='0';
next_state<=state10;
when state10=>
data <='0';
next_state<=state1;

end case;
end process;

end Behavioral;

I m using '0' as start bit , '0' as stop bit and 8 data bits. I am transmitting each bit for 4 clock cycle. If this code is correct and will transmit some data on hyperterminal?
please reply.

 

[nupurs]

Re: vhdl code for serial port

I have written this VHDL code for serial transmission ................


entity serial_tx is
Port ( clk : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC);
end serial_tx;

architecture Behavioral of serial_tx is
signal clkout:std_logic:='0';
signal data:std_logic:='0';
signal count:integer:=0;
type state is(state1,state2,state3,state4,state5,state6,state7,state8,state9,state10);
signal current_state,next_state:state;
begin
process(clk)
begin
if clk'event and clk='1' then
count<=count + 1;
TxD <= data;
if count =4 then
clkout<= not clkout;
count<=0;
end if;
end if;
end process;

process(clkout)
begin
current_state<=next_state;
end process;

process(current_state,next_state)
begin
case current_state is
when state1=>
data <='0';
next_state<=state2;
when state2=>
data <='0';
next_state<=state3;
when state3=>
data <='1';
next_state<=state4;
when state4=>
data <='0';
next_state<=state5;
when state5=>
data <='0';
next_state<=state6;
when state6=>
data <='0';
next_state<=state7;
when state7=>
data <='0';
next_state<=state8;
when state8=>
data <='1';
next_state<=state9;
when state9=>
data <='0';
next_state<=state10;
when state10=>
data <='0';
next_state<=state1;

end case;
end process;

end Behavioral;

I m using '0' as start bit , '0' as stop bit and 8 data bits. I am transmitting each bit for 4 clock cycle. If this code is correct and will transmit some data on hyperterminal?
please reply.

i am trying to interface fpga with gsm sim300 .can ny one help on how to program the fpga for serial communication with gsm?

 

[mrflibble]

For the serial interface: https://www.fpga4fun.com/SerialInterface.html

For the actual data you send over that serial interface: code you are about to write.

 

[nupurs]

thanks a lot for your help

- - - Updated - - -

did this code work for you?

 

[mrflibble]

Yes it did work for me. All I had to do was change the parameters for system clock and baud rate.