vhdl code for real time clock

[mohan_ece]

i need vhdl code for real time clock.
plz send soon
very urgent.

 

[jearome]

a real time clock?
a crystal oscillator is ok

 

[jimmy_tag]

Check this out, I have posted it on my Blog. its completely synthesizable. You can also check its video.

VHDL codes: Synthesizable RTC in VHDL

 

[vipinlal]

See if this helps:
VHDL coding tips and tricks: Digital clock in VHDL

The code has the following outputs, seconds,minutes and hours.The input clock is 100MHz. but the code can be easily modified for any other freq.

 

[permute]

Perhaps you forgot to simulate that one? The seconds/minutes will count 58 59 60 1 instead of 58 59 0 1.

I think you meant to use variables and blocking assignments, but used signals and non-blocking assingments.

 

[vipinlal]

permute, I do agree. There is a small mistake in there. Will change it soon.
thanks.

 

[permute]

That's one of my main complaints about VHDL -- "variables" don't have nonblocking assigns, and signals can't be declared local to a process. The main drive for variables is simulation performance, but the lack of nonblocking assigns means there are location-dependence on the assignments that doesn't exist for signals/ports. Its annoying because variables with blocking assigns carry a lot of annoying catches when properly used to infer simple logic, and will accidently infer complex logic when the developer makes mistakes. Such is not a syntax error or DRC issue. The alternative is to forgo variables and accept lower simulation performance (and get readable code where its clear what the code infers by a simple glance).

I've seen various coding "standards". Ones that are focused on reuse will emphasize never using variables (inside processes), as there are issues with the need to mix blocking/non-blocking assigns. Ones focused on simulation will focus on only using variables as such can give performance advantages (in terms of sim).

 

[FvM]

There is a small mistake in there. Will change it soon.

Not a small mistake. The counter carry logic is completely erronous.

process(clk)   --period of clk is 1 second.
begin
if(clk'event and clk='1') then
sec <= sec+ 1;
if(sec = 59) then
min <= min + 1;
end if;
if(min = 60) then
hour <= hour + 1;
min <= 1;
end if;
if(hour = 24) then
hour <= 0;
end if;
if(sec = 60) then
sec <= 1;
end if;
end if;
end process;

Should be coded like this:

sec <= sec+ 1;
if(sec = 59) then
  sec <= 0;
  min <= min + 1;
  if(min = 59) then
    min <= 0;
    hour <= hour + 1;
    if(hour = 23) then
      hour <= 0;
    end if;
  end if;
end if;

Regarding permute's comment on possible usage of blocking statements. The above suggested carry logic, written by "non-blocking" signal assignments represents the actual logic wiring of a synchronous counter. It can be expressed in a C-like procedural style with "blocking" variable assignments. It's possibly more intuitive to programmers that have difficulties to think in hardware structures. But it's not the way the synthesized design works, the design compiler has to translate it in a "non-blocking" gate level net list.

As a final comment. VHDL for synthesis would usually implement the seconds tic as a clock enable rather than a ripple clock to avoid timing issues.

P.S.: A more verbose form of the code can emphasize the actual register assignment operation

if(sec < 59) then
  sec <= sec+ 1;
else
  sec <= 0;
  if(min < 59) then
    min <= min + 1;
  else
    min <= 0;
    if(hour < 23) then
      hour <= hour + 1;
    else
      hour <= 0;
    end if;
  end if;
end if;

 

[vipinlal]

I agree, FvM.

Please check the modified code:
VHDL coding tips and tricks: Digital clock in VHDL

 

[jimmy_tag]

Check this out, I have posted it on my Blog. its completely synthesizable. You can also check its video.

VHDL codes: Synthesizable RTC in VHDL

Check out my updated code for RTC with manual hr and min set.

VHDL CODES: RTC with manual hr and min set