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for example if you work the FPGA or CPLD on 50Mhz you will make clock divider to get the 40Mhz which will operate the ADC
and then make process with sensetivity list on (input clock and the input data from ADC)
this process will operate when the rising edge of clk or the variation in the input from ADC and then save this data in buffer and so ...
if you work by verilog replace process to always
hi.. If u r using an FPGA starter kit u may find ADC & DAC already existing in the kit...then all u have to do is to enable it by using SPI interface i think.. u'd better check the user guide i guess.. i hope this what u need.
I have a similar project wherein :
1.There is an onboard ADC in Altera fpga Stratix II EP2S180 kit, to accept analog waveform.
2.The ADC output has to be digitally amplified by the vhdl code dumped in fpga.
3.The amplified output goes to DAC and outputted.