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how to create matrix in vhdl...and how to access ...how to access each value..
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Code VHDL - [expand] 1 2 3 4 5 6 --declaration type a1 is array (0 to 7, 0 to 7) of std_logic; signal ar :a1; -- Declaration of an array --to access ar(0,0) <= '1'; -- this will set first element to 1
Code VHDL - [expand] 1 2 3 4 5 6 7 8 --declaration type a1 is array (0 to 7) of std_logic_vector(0 to 7); signal ar :a1; -- Declaration of an array signal arr : a1 :=(others=>(others=>'0')); -- Initialization of array --to access ar(0)(0) <= '1'; -- this will set first element to 1 arr(1) <= "01101000"; -- this will set the row1 to the byte given...