VHDL automated test bench

Status
Not open for further replies.
J

jigjack

Member level 1
Joined
Aug 5, 2004
Messages
35
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
319
hi all,

can someone give me an example of using VHDL for creating a fully automated test environment... that includes protocol checking and scorebording ...

i would also like to learn more about creating the same for verilog.

thanks in advance.
 

jigjack said:
hi all,

can someone give me an example of using VHDL for creating a fully automated test environment... that includes protocol checking and scorebording ...

i would also like to learn more about creating the same for verilog.

thanks in advance.
Click to expand...
Take a look at SystemVerilog features, capabilities. A recent book has shown a decent complete example with a sophasticated TB. See:
**broken link removed** for more.

HTH
Aji
http://www.noveldv.com
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…