makanaky
Advanced Member level 4
Hi ,
I am using the folowing VHDL code and i get the error message on modelsim although the condition in the assert statement is fullfilled , any advice please ?
i get this in modelsim :
# ** Error: problem
# Time: 100 ns Iteration: 0 Instance: /alu_tb
# ** Error: problem
# Time: 105 ns Iteration: 0 Instance: /alu_tb
# ** Error: problem
# Time: 110 ns Iteration: 0 Instance: /alu_tb
# ** Error: problem
# Time: 115 ns Iteration: 0 Instance: /alu_tb
I am using the folowing VHDL code and i get the error message on modelsim although the condition in the assert statement is fullfilled , any advice please ?
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
sel : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
process (sel,a,b,cin)
begin
if sel(3)='0' then
case sel is
when "0000" => y<=a ;
when "0001" => y<=a+1 ;
when "0010" => y<=a-1 ;
when "0011" => y<=b ;
when "0100" => y<=b+1 ;
when "0101" => y<=b-1 ;
when "0110" => y<=a+b ;
when "0111" => y<=a+b+Cin ;
when others => y<="ZZZZZZZZ" ;
end case;
elsif sel(3)='1' then
case sel is
when "1000" => y<=not a ;
when "1001" => y<=not b ;
when "1010" => y<=a and b ;
when "1011" => y<=a or b ;
when "1100" => y<=a nand b ;
when "1101" => y<=a nor b;
when "1110" => y<=a xor b ;
when "1111" => y<=a xnor b ;
when others => y<="ZZZZZZZZ" ;
end case;
end if;
end process;
end Behavioral;
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY ALU_TB IS
END ALU_TB;
ARCHITECTURE behavior OF ALU_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
sel : IN std_logic_vector(3 downto 0);
cin : IN std_logic;
y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(7 downto 0) := (others => '0');
signal b : std_logic_vector(7 downto 0) := (others => '0');
signal sel : std_logic_vector(3 downto 0) := (others => '0');
signal cin : std_logic := '0';
signal clk : std_logic;
--Outputs
signal y : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
a => a,
b => b,
sel => sel,
cin => cin,
y => y
);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
wait for 100ns;
-- insert stimulus here
sel<="0000";
a<="00001101";
b<="00000000";
cin<='1';
assert y="00001101"
Report "problem"
severity error ;
wait for 5 ns ;
sel<="0001";
a<="00001101";
b<="00000000";
cin<='0';
assert y="00001110"
Report "problem"
severity error ;
wait for 5 ns ;
sel<="0010";
a<="00001101";
b<="00000010";
cin<='1';
assert y="00001100"
Report "problem"
severity error ;
wait for 5 ns ;
sel<="0011";
a<="00001101";
b<="00000011";
cin<='1';
assert y="00000011"
Report "problem"
severity error ;
wait for 5 ns ;
wait;
end process;
END;
i get this in modelsim :
# ** Error: problem
# Time: 100 ns Iteration: 0 Instance: /alu_tb
# ** Error: problem
# Time: 105 ns Iteration: 0 Instance: /alu_tb
# ** Error: problem
# Time: 110 ns Iteration: 0 Instance: /alu_tb
# ** Error: problem
# Time: 115 ns Iteration: 0 Instance: /alu_tb