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VHDL assert statement error

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makanaky

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Hi ,

I am using the folowing VHDL code and i get the error message on modelsim although the condition in the assert statement is fullfilled , any advice please ?

Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU is
    Port ( a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
           sel : in  STD_LOGIC_VECTOR (3 downto 0);
           cin : in  STD_LOGIC;
           y : out  STD_LOGIC_VECTOR (7 downto 0));
end ALU;

architecture Behavioral of ALU is

begin
process (sel,a,b,cin)
begin
if sel(3)='0' then
case sel is
when "0000" => y<=a ;
when "0001" => y<=a+1 ;
when "0010" => y<=a-1 ;
when "0011" => y<=b ;
when "0100" => y<=b+1 ;
when "0101" => y<=b-1 ;
when "0110" => y<=a+b ;
when "0111" => y<=a+b+Cin ;
when others => y<="ZZZZZZZZ" ;

end case;
elsif sel(3)='1' then 
case sel is
when "1000" => y<=not a ;
when "1001" => y<=not b ;
when "1010" => y<=a and b ;
when "1011" => y<=a or b ;
when "1100" => y<=a nand b ;
when "1101" => y<=a nor b;
when "1110" => y<=a xor b ;
when "1111" => y<=a xnor b ;
when others => y<="ZZZZZZZZ" ;
end case;
end if;
end process;

end Behavioral;

Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY ALU_TB IS
END ALU_TB;
 
ARCHITECTURE behavior OF ALU_TB IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ALU
    PORT(
         a : IN  std_logic_vector(7 downto 0);
         b : IN  std_logic_vector(7 downto 0);
         sel : IN  std_logic_vector(3 downto 0);
         cin : IN  std_logic;
         y : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal a : std_logic_vector(7 downto 0) := (others => '0');
   signal b : std_logic_vector(7 downto 0) := (others => '0');
   signal sel : std_logic_vector(3 downto 0) := (others => '0');
   signal cin : std_logic := '0';
	signal clk : std_logic;

 	--Outputs
   signal y : std_logic_vector(7 downto 0);
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: ALU PORT MAP (
          a => a,
          b => b,
          sel => sel,
          cin => cin,
          y => y
        );
 
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
   
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.
      wait for 100ns;	

    

      -- insert stimulus here 
		
		sel<="0000";
		a<="00001101";
		b<="00000000";
		cin<='1';
		assert y="00001101"
		Report "problem"
		severity error ;
		
		wait for 5 ns ;
		
		sel<="0001";
		a<="00001101";
		b<="00000000";
		cin<='0';
		assert y="00001110"
		Report "problem"
		severity error ;
		
		wait for 5 ns ;
		
		sel<="0010";
		a<="00001101";
		b<="00000010";
		cin<='1';
		assert y="00001100"
		Report "problem"
		severity error ;
		
		wait for 5 ns ;
		
		sel<="0011";
		a<="00001101";
		b<="00000011";
		cin<='1';
		assert y="00000011"
		Report "problem"
		severity error ;
		
		wait for 5 ns ;

      wait;
   end process;

END;

i get this in modelsim :


# ** Error: problem
# Time: 100 ns Iteration: 0 Instance: /alu_tb
# ** Error: problem
# Time: 105 ns Iteration: 0 Instance: /alu_tb
# ** Error: problem
# Time: 110 ns Iteration: 0 Instance: /alu_tb
# ** Error: problem
# Time: 115 ns Iteration: 0 Instance: /alu_tb
 

FvM

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As expectable. y won't be updated before the next delta cycle because you're in a sequential process.
 

makanaky

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Thanks it worked , can you please just make things clearer for me , just correct me if I am wrong :

the output y is updated only after the wait statemet ( after 5 ns ) ? if yes why did the waveforms of y appear to be updated instantly ?
 

TrickyDicky

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Its to do with the mechanics of VHDL. VHDL works on delta cycles, which are infinitly small amounts of time. Each assignment to a signal is not actually done until the next delta cycle. So if you did this:

Code:
b <= a;
c <= b;
d <= c;

process(a)
begin
  assert d= c report "D is not equal to C" severity failure;
end process;

You would always get an error because b gets updated 1 delta before c, and c gets updated 1 delta before d. So when A changes, its 3 deltas until D equals A.
The way to wait for a single delta is

wait for 0 ns;

But because deltas are infinitely short, on the waveform it looks instant.
 
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FvM

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Normally, without any wait statements, all left-hand sides of signal assignments in a sequential block are updated at it's end, in this case after end process. The wait causes an immediate update.
 

makanaky

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I see , so the signals are updated at the wait statement itself ( not after 5 ns in case of "wait for 5ns" ) , right ?
 

TrickyDicky

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signals only get scheduled to be updated. They update when the process they are assigned in suspends (like when you hit a wait statement).

This is in contrast to variables, that are updated immediatly.
 
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