LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY ALU_TB IS
END ALU_TB;
ARCHITECTURE behavior OF ALU_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
sel : IN std_logic_vector(3 downto 0);
cin : IN std_logic;
y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(7 downto 0) := (others => '0');
signal b : std_logic_vector(7 downto 0) := (others => '0');
signal sel : std_logic_vector(3 downto 0) := (others => '0');
signal cin : std_logic := '0';
signal clk : std_logic;
--Outputs
signal y : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
a => a,
b => b,
sel => sel,
cin => cin,
y => y
);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
wait for 100ns;
-- insert stimulus here
sel<="0000";
a<="00001101";
b<="00000000";
cin<='1';
assert y="00001101"
Report "problem"
severity error ;
wait for 5 ns ;
sel<="0001";
a<="00001101";
b<="00000000";
cin<='0';
assert y="00001110"
Report "problem"
severity error ;
wait for 5 ns ;
sel<="0010";
a<="00001101";
b<="00000010";
cin<='1';
assert y="00001100"
Report "problem"
severity error ;
wait for 5 ns ;
sel<="0011";
a<="00001101";
b<="00000011";
cin<='1';
assert y="00000011"
Report "problem"
severity error ;
wait for 5 ns ;
wait;
end process;
END;