#### hitx

##### Member level 2

Why I always get an error for signal operation (bold part of the codes) for the VHDL codes below .. Thanks now

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main_REAL is

port (

SW : in std_logic;

result : out std_logic_vector (7 downto 0)

);

end main_REAL;

architecture Behavioral of main_REAL is

signal int : integer;

begin

process (SW)

variable Xn : real;

variable i : integer;

begin

Xn := 0.25;

i := 1;

while i <= 1 loop

**Xn := 4 * Xn * (1-Xn);**

i := i + 1;

end loop;

int <= integer (Xn*100);

result <= conv_std_logic_vector (int, 8);

end process;

end Behavioral;