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[SOLVED] VHDL arithmetic operation for signal

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hitx

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Hi dear friends,

Why I always get an error for signal operation (bold part of the codes) for the VHDL codes below .. Thanks now

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main_REAL is
port (
SW : in std_logic;
result : out std_logic_vector (7 downto 0)

);
end main_REAL;

architecture Behavioral of main_REAL is
signal int : integer;

begin
process (SW)
variable Xn : real;
variable i : integer;
begin
Xn := 0.25;
i := 1;
while i <= 1 loop
Xn := 4 * Xn * (1-Xn);
i := i + 1;
end loop;
int <= integer (Xn*100);
result <= conv_std_logic_vector (int, 8);
end process;
end Behavioral;
 

what is the error?
you may need to change it to 4.0 * Xn * (1.0 - Xn)

PS. I assume this is some simulation code - you cannot compile this for an FPGA as real types and while loops are not synthesisable.
 

The error is " * can not have such operands in this context." . I used Xn as a signal, but nothing changed. Where am I wrong?

By the way, thanks for response my friend.
 

did you try my changes? using 4 and 1 rather than 4.0 and 1.0 makes it think they are integers. you also need to change the 100 to 100.0 (do you understand the differences here?
 

Thanks my friend, I solved the problem.

Take care..

Bye
 

Thanks my friend, I solved the problem.
Did you, or did TrickyDicky solve the problem with his suggestion above ? That information would help others experiencing the same problem, which is after all, the whole point of forums/mailing lists. So please state exactly how the problem was solved. Thanks.
 

You are definitely right my dear friend, robiwan. In fact, there is a problem about the fixed and float package library. Then , I have noticed that situation. But again thanks alot for the help from TrickyDicky. The other error is related with the suggestion from TrickyDicky. Thanks will not be enough against your help. Is this sentence logical ??? :):) Anyway, take care my all friends..

Best Regards
 

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