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| entity SampleEntity is
port(clk, reset : in std_logic;
start, dataIn : in std_logic;
ready, dataOut: out std_logic;);
end SampleEntity;
architecture Arch of SampleEntity is
type State is (IDLE, INIT, CONF, READY_STATE, BUSY);
signal currentState_reg, currentState_next: State;
signal INIT_start, INIT_done, INIT_data: std_logic;
signal CONF_start, CONF_ready, CONF_done, CONF_data: std_logic;
signal CMDR_start, CMDR_ready, CMDR_dataI, CMDR_dataO: std_logic;
begin
P_INIT: entity work.Predefined_INIT(Arch)
port map (--ins
clk => clk, reset => reset,
start => INIT_start,
--outs
done => INIT_done, data => INIT_data);
P_CONF: entity work.Predefined_CONF(Arch)
port map (--ins
clk => clk, reset => reset,
start => CONF_start, ready => CONF_ready,
--outs
done => CONF_done, data => CONF_data);
P_CMDR: entity work.Predefined_CMDR(Arch)
port map (--ins
clk => clk, reset => reset,
start => CMDR_start, dataI => CMDR_dataI,
--outs
ready => CMDR_ready, dataO => CMDR_dataO);
-- Sync state transitions with clk
Synchro: process(clk, reset)
begin
if reset='1' then
currentState_reg <= IDLE;
elsif rising_edge(clk) then
currentState_reg <= currentState_next;
end if;
end process Synchro;
-- Next-state logic
NextState: process(start, dataIn, currentState_reg,
INIT_done, INIT_data,
CONF_done, CONF_start, CONF_data,
CMDR_ready , CMDR_dataO)
begin
-- Default values
currentState_next <= currentState_reg;
-- Interprocess signals
INIT_start <= '0';
CONF_start <= '0'; CONF_ready <= '0';
CMDR_start <= '0'; CMDR_dataI <= '0';
-- port outs
ready <= '0'; dataOut <= '0';
case currentState_reg is
when IDLE =>
-- Stay IDLE until user sends enable.
if start='1' then
currentState_next <= INIT;
end if;
when INIT =>
-- Send start signal to P_INIT.
INIT_start <= '1';
-- Send P_INIT data to port dataOut
dataOut <= INIT_data;
-- Stay INIT until P_INIT says done.
if INIT_done='1' then
-- Send start signal to P_CONF and P_CMDR
CONF_start <= '1';
CMDR_start <= '1';
currentState_next <= CONF;
end if;
when CONF =>
-- Send P_CMDR ready to P_CONF
CONF_ready <= CMDR_ready;
-- Send P_CONF data to P_CMDR
CMDR_start <= CONF_start;
CMDR_dataI <= CONF_data;
-- Stay CONF until P_CONF says done.
if CONF_done='1' then
currentState_next <= READY_STATE;
end if;
when READY_STATE =>
-- Send P_CMDR ready to port ready
ready <= CMDR_ready;
-- Stay in READY_STATE until port starts new dataIn.
if start='1' then
-- Send port start & dataIn to P_CMDR
CMDR_start <= start;
CMDR_dataI <= dataIN;
currentState_next <= BUSY;
end if;
when BUSY =>
-- Send P_CMDR dataO to port dataOut
dataOut <= CMDR_dataO
-- Stay in BUSY_STATE until P_CMDR says ready.
if CMDR_ready='1' then
currentState_next <= READY_STATE;
end if;
end case;
end process NextState;
end architecture Arch; |