Very Low transition fault coverage, please help

[dianin]

I'm getting very low transition fault coverage (56%). The tool is cadence's Encounter Test which is pretty new to me. Could anybody suggest how to debug it. What could be the cause of low coverage. The stuck-at fault coverage is around 97%.

 

[maulin sheth]

Generally Stuck coverage is 95+..so For Stuck at your coverage is fine...
And for Transition : generally : 80+..But In your case, coverage is 56% only...
So for that you need to analyze the faults which are not detected...There are some fault categories...in Which we need to concentrate for improving the test coverage....
So the categories are like : Detected, ATPG Untestable, Not Controlled, Not observed etc....so you need to generate the report for the faults which are not detected....
That information you will gen in the ATPG tool user guide itself...

 

[ajukrishnan]

Make sure that you clear the D1, D2, D3, D9 violations to ensure that all flops are converted to scan flops. Modulewise, you need to write out the ND(undetectable faults) as well as the AU (ATPG untestable). If AU faults are more, then you need increase the abort limit.
If latches in the module are not transparent, then they must be made transparent. For this, you must OR the latch-enable signal from logic with the dft test_enable signal.
report the non-scannable flops for the module based on the clock domain. If the non-scannable flops are more, then we can increase the capture cycles, so that these elements can also be loaded.

 

[dianin]

Thanks for the inputs.

There is no D1/2/3/9 violation in my design. All the flops are scannable flops. Could anyone explain why there is a huge coverage difference in stuck-at and transition fault (besides the clock frequency)

 

[maulin sheth]

The solution is that : You need to analyze it....why the fault coverage is less? What are the sources of less coverage?