abu9022
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HI friends,
can you please Help me, how to solve the following error in modelsim
Loading work.iu_verilog1
** Error: (vsim-3033) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_verilog1.v(31): Instantiation of 'iu_syn_updated' failed. The design unit was not found.
Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1
Searched libraries:
/mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/work
I am adding two files below:
iu_verilog1.v
- - - Updated - - -
second file
iu_syn_updated.v
I added only module mentioned in netlist
can you please Help me, how to solve the following error in modelsim
Loading work.iu_verilog1
** Error: (vsim-3033) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_verilog1.v(31): Instantiation of 'iu_syn_updated' failed. The design unit was not found.
Region: /tbleon/tb/p0/leon0/mcore0/proc0/iu0/iu1
Searched libraries:
/mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/work
I am adding two files below:
iu_verilog1.v
Code:
//`timescale 1ns/10ps
module iu_verilog1(rst, clk, te, holdn, ici, ico, dci, dco, fpui, fpuo, iui, iuo, rfi, rfo, cpi, cpo, fpi, fpo);
input rst, clk, te, holdn;
output [94:0] ici;
input [68:0] ico;
output [116:0] dci;
input [127:0] dco;
output [145:0] fpui;
input [74:0] fpuo;
input [66:0] iui;
output [517:0] iuo;
output [58:0] rfi;
input [63:0] rfo;
output [392:0] cpi;
input [172:0] cpo;
output [392:0] fpi;
input [172:0] fpo;
wire [94:0] ici;
wire [116:0] dci;
wire [145:0] fpui;
wire [517:0] iuo;
wire [58:0] rfi;
wire [392:0] cpi;
wire [392:0] fpi;
//reg my_clk1, my_clk2;
iu_syn_updated iu2(rst, clk, te, holdn, ici, ico, dci, dco, fpui, fpuo, iui, iuo, rfi, rfo, cpi, cpo, fpi, fpo);
initial begin
// $monitor(clk, $time, $realtime);
$set_gate_level_monitoring("rtl_on");
$set_toggle_region(iu_verilog1.iu2);
$toggle_start;
// #10000
#3000000000
//#1000
$toggle_stop;
$toggle_report("basicMathSmall3nsPeriod3SecondRun.saif",1.0e-9,"iu_verilog1.iu2");
// $dumpfile("mul.vcd");
// $dumpvars(0,test_multiplier.mul);
// $dumpvars;
end
//initial begin
// $dumpfile("stringSearch.vcd");
// $dumpvars(0,iu_verilog1.iu2);
//end
//initial begin
// $sdf_annotate("./final.sdf",iu2);
//end
endmodule
- - - Updated - - -
second file
iu_syn_updated.v
Code:
module iu ( rst, clk,te, holdn, .ici({\ici[RPC][31] , \ici[RPC][30] ,
\ici[RPC][29] , \ici[RPC][28] , \ici[RPC][27] , \ici[RPC][26] ,
\ici[RPC][25] , \ici[RPC][24] , \ici[RPC][23] , \ici[RPC][22] ,
\ici[RPC][21] , \ici[RPC][20] , \ici[RPC][19] , \ici[RPC][18] ,
\ici[RPC][17] , \ici[RPC][16] , \ici[RPC][15] , \ici[RPC][14] ,
\ici[RPC][13] , \ici[RPC][12] , \ici[RPC][11] , \ici[RPC][10] ,
\ici[RPC][9] , \ici[RPC][8] , \ici[RPC][7] , \ici[RPC][6] ,
\ici[RPC][5] , \ici[RPC][4] , \ici[RPC][3] , \ici[RPC][2] ,
\ici[FPC][31] , \ici[FPC][30] , \ici[FPC][29] , \ici[FPC][28] ,
\ici[FPC][27] , \ici[FPC][26] , \ici[FPC][25] , \ici[FPC][24] ,
\ici[FPC][23] , \ici[FPC][22] , \ici[FPC][21] , \ici[FPC][20] ,
\ici[FPC][19] , \ici[FPC][18] , \ici[FPC][17] , \ici[FPC][16] ,
\ici[FPC][15] , \ici[FPC][14] , \ici[FPC][13] , \ici[FPC][12] ,
\ici[FPC][11] , \ici[FPC][10] , \ici[FPC][9] , \ici[FPC][8] ,
I added only module mentioned in netlist