pandit_vlsi
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verilogout_no_tri
hi all.
i am not following what this cmmanr will do.
verilogout_no_tri
Declares three-state nets as Verilog "wire" instead of "tri." This variable is
useful in eliminating "assign" primitives and "tran" gates in the Verilog output.
hi all.
i am not following what this cmmanr will do.
verilogout_no_tri
Declares three-state nets as Verilog "wire" instead of "tri." This variable is
useful in eliminating "assign" primitives and "tran" gates in the Verilog output.
