VerilogA timer problem

[upasana sahu]

Hello,

I am trying to write verilog-A code to model a circuit that acts as an analog timer.
By default, the output is low .Then calculate time (t) and the output should be high for a constant time (t+delt) then it goes low again and repeat it

Any help?

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Code Verilog - [expand]
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module Neuron16Jan(IN1,IN2,R1,G1);
input IN1,IN2;
output R1;
output G1;
electrical IN1,IN2,G1;
electrical gnd; //internal port
electrical R1;
parameter real slope_velocity_vs_currentdensity=0.11;
parameter real vlogic_low=225e-3;
parameter real vlogic_high=703e-3;
parameter real total_distance=5800e-9;
parameter real delt=209n;
real t;
real t1;
integer temp,next;
analog begin
V(gnd)<+0;
t=(total_distance)/((slope_velocity_vs_currentdensity)*(I(IN1,gnd)+I(IN2,gnd))*1e6);
t1=((total_distance)/((slope_velocity_vs_currentdensity)*(I(IN1,gnd)+I(IN2,gnd))*1e6))+209n;
@(initial_step) begin
temp=0;
end
 
@(timer(t)) begin
temp=0;
end
@(timer(t,t1)) begin
temp=1;
end
V(R1)<+ transition(temp ? vlogic_high:vlogic_low,0.01n,0.01n);
end
endmodule

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