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Verilog-XL compile problem

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kvsim

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Dear all:
I have module abc in both filea, fileb and filec , is there any method to compile module abc in fileb, other than modify filea and filec.
Thx!
 

aji_vlsi

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kvsim said:
Dear all:
I have module abc in both filea, fileb and filec , is there any method to compile module abc in fileb, other than modify filea and filec.
Thx!

Try:
Code:
  verilog fileb -v filea -v filec

Essentially you make filea and filec as library files that will be looked up iff required.

HTH
Ajeetha, CVC
www.noveldv.com
 

kvsim

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well, It works.
there is another question: If cell A has a hierachical cell B in library lib_a, there is a cell name B in library lib_b too, how could I make the cell B in lib_b priority ( Let Verilog-XL compiler using cell B in lib_b, not the cell B in lib_a)

Thanks & Best Regards
 

aji_vlsi

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kvsim said:
well, It works.
there is another question: If cell A has a hierachical cell B in library lib_a, there is a cell name B in library lib_b too, how could I make the cell B in lib_b priority ( Let Verilog-XL compiler using cell B in lib_b, not the cell B in lib_a)

Thanks & Best Regards

What you need is Verilog 2001's configuration to do this. Not sure if VXL supports it, NC should support, why are you using VXL? I thought that was close to be End of life?

Regards
Ajeetha, CVC
www.noveldv.com
 

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