damdam23
Newbie level 3
Hi,
I am trying to understand a piece of Verilog code as below:
module_name instance_name ( ..... .signal1(signal1_local['SIGNAL_WIDTH - 1 : 0]), .... );
or in
wire [`SIGNAL_WIDTH - 1 : 0] signal1;
I am not able to understand the 'SIGNAL_WIDTH , why is the apostrophe (') used here? Can anyone please tell me what does it signify? Thanks in advance
I am trying to understand a piece of Verilog code as below:
module_name instance_name ( ..... .signal1(signal1_local['SIGNAL_WIDTH - 1 : 0]), .... );
or in
wire [`SIGNAL_WIDTH - 1 : 0] signal1;
I am not able to understand the 'SIGNAL_WIDTH , why is the apostrophe (') used here? Can anyone please tell me what does it signify? Thanks in advance