Verilog : Use of 'PARAMETER while declaring signals,instantiations,etc

[damdam23]

Hi,

I am trying to understand a piece of Verilog code as below:
module_name instance_name ( ..... .signal1(signal1_local['SIGNAL_WIDTH - 1 : 0]), .... );
or in
wire [`SIGNAL_WIDTH - 1 : 0] signal1;

I am not able to understand the 'SIGNAL_WIDTH , why is the apostrophe (') used here? Can anyone please tell me what does it signify? Thanks in advance

 

[hirenpatel]

i think `SIGNAL_WIDTH is define above in the program so it is used with apostrophe (`)....

 

[imbichie]

This is nothing but a verilog macro, see the below definition:

`define Macro Substitution
The `define compiler directive is used to perform "global" macro substitution, similar to the C-language
#define directive. Macro substitutions are global from the point of definition and remain active for all files read after
the macro definition is made or until another macro definition changes the value of the defined macro or until
the macro is undefined using the `undef compiler directive.
Macro definitions can exist either inside or outside of a module declaration, and both are treated the same.
parameter declarations can only be made inside of module boundaries.
Since macros are defined for all files read after the macro definition, using macro definitions generally makes
compiling a design file-order dependent.
A typical problem associated with using macro definitions is that another file might also make a macro
definition to the same macro name. When this occurs, Verilog compilers issue warnings related to "macro
redefinition" but an unnoticed warning can be costly to the design or to the debug effort.

Example:
`define CYCLE 10
module tb_cycle;
// ...
initial begin
clk = 1'b0;
forever #(`CYCLE/2) clk = ~clk;
end
// ...
endmodule