Verilog Tree Comparator

Adix149 · Feb 26, 2011

Hi, I m trying to simulate a tree type comparator for synthesis. It has two blocks and i used repetitive tasks to achieve it. But my test bench is showing errors . Can anybody try this

Code:

module main_fn (A,B,G,L,E,g,l,e);
  input [31:0] A;
  input [31:0] B; 
  output [61:0]g;
  output [61:0]l;
  output [61:0]e;
  wire G_temp,E_temp,L_temp;
  output G,L,E;

  compare1 cp1_1(A[0],B[0],g[0],l[0],e[0]);
  compare1 cp1_2(A[l],B[l],g[1],l[1],e[1]);
  compare1 cp1_3(A[2],B[2],g[2],l[2],e[2]);
  compare1 cp1_4(A[3],B[3],g[3],l[3],e[3]);
  compare1 cp1_5(A[4],B[4],g[4],l[4],e[4]);
  compare1 cp1_6(A[5],B[5],g[5],l[5],e[5]);
  compare1 cp1_7(A[6],B[6],g[6],l[6],e[6]);
  compare1 cp1_8(A[7],B[7],g[7],l[7],e[7]);
  compare1 cp1_9(A[8],B[8],g[8],l[8],e[8]);
  compare1 cp1_10(A[9],B[9],g[9],l[9],e[9]);
  compare1 cp1_11(A[10],B[10],g[10],l[10],e[10]);
  compare1 cp1_12(A[11],B[11],g[11],l[11],e[11]);
  compare1 cp1_13(A[12],B[12],g[12],l[12],e[12]);
  compare1 cp1_14(A[13],B[13],g[13],l[13],e[13]);
  compare1 cp1_15(A[14],B[14],g[14],l[14],e[14]);
  compare1 cp1_16(A[15],B[15],g[15],l[15],e[15]);
  compare1 cp1_17(A[16],B[16],g[16],l[16],e[16]);
  compare1 cp1_18(A[17],B[17],g[17],l[17],e[17]);
  compare1 cp1_19(A[18],B[18],g[18],l[18],e[18]);
  compare1 cp1_20(A[19],B[19],g[19],l[19],e[19]);
  compare1 cp1_21(A[20],B[20],g[20],l[20],e[20]);
  compare1 cp1_22(A[21],B[21],g[21],l[21],e[21]);
  compare1 cp1_23(A[22],B[22],g[22],l[22],e[22]);
  compare1 cp1_24(A[23],B[23],g[23],l[23],e[23]);
  compare1 cp1_25(A[24],B[24],g[24],l[24],e[24]);
  compare1 cp1_26(A[25],B[25],g[25],l[25],e[25]);
  compare1 cp1_27(A[26],B[26],g[26],l[26],e[26]);
  compare1 cp1_28(A[27],B[27],g[27],l[27],e[27]);
  compare1 cp1_29(A[28],B[28],g[28],l[28],e[28]);
  compare1 cp1_30(A[29],B[29],g[29],l[29],e[29]);
  compare1 cp1_31(A[30],B[30],g[30],l[30],e[30]);
  compare1 cp1_32(A[31],B[31],g[31],l[31],e[31]);

  compare2 cp2_1(g[0],g[1],l[0],l[1],e[0],e[1],g[32],l[32],e[32]);
  compare2 cp2_2(g[2],g[3],l[2],l[3],e[2],e[3],g[33],l[33],e[33]);
  compare2 cp2_3(g[4],g[5],l[4],l[5],e[4],e[5],g[34],l[34],e[34]);
  compare2 cp2_4(g[6],g[7],l[6],l[7],e[6],e[7],g[35],l[35],e[35]);
  compare2 cp2_5(g[8],g[9],l[8],l[9],e[8],e[9],g[36],l[36],e[36]);
  compare2 cp2_6(g[10],g[11],l[10],l[11],e[10],e[11],g[37],l[37],e[37]);
  compare2 cp2_7(g[12],g[13],l[12],l[13],e[12],e[13],g[38],l[38],e[38]);
  compare2 cp2_8(g[14],g[15],l[14],l[15],e[14],e[15],g[39],l[39],e[39]);
  compare2 cp2_9(g[16],g[17],l[16],l[17],e[16],e[17],g[40],l[40],e[40]);
  compare2 cp2_10(g[18],g[19],l[18],l[19],e[18],e[19],g[41],l[41],e[41]);
  compare2 cp2_11(g[20],g[21],l[20],l[21],e[20],e[21],g[42],l[42],e[42]);
  compare2 cp2_12(g[22],g[23],l[22],l[23],e[22],e[23],g[43],l[43],e[43]);
  compare2 cp2_13(g[24],g[25],l[24],l[25],e[24],e[25],g[44],l[44],e[44]);
  compare2 cp2_14(g[26],g[27],l[26],l[27],e[26],e[27],g[45],l[45],e[45]);
  compare2 cp2_15(g[28],g[29],l[28],l[29],e[28],e[29],g[46],l[46],e[46]);
  compare2 cp2_16(g[30],g[31],l[30],l[31],e[30],e[31],g[47],l[47],e[47]);
  
  compare2 cp3_1(g[32],g[33],l[32],l[33],e[32],e[33],g[48],l[48],e[48]);
  compare2 cp3_2(g[34],g[35],l[34],l[35],e[34],e[35],g[49],l[49],e[49]);
  compare2 cp3_3(g[36],g[37],l[36],l[37],e[36],e[37],g[50],l[50],e[50]);
  compare2 cp3_4(g[38],g[39],l[38],l[39],e[38],e[39],g[51],l[51],e[51]);
  compare2 cp3_5(g[40],g[41],l[40],l[41],e[40],e[41],g[52],l[52],e[52]);
  compare2 cp3_6(g[42],g[43],l[42],l[43],e[42],e[43],g[53],l[53],e[53]);
  compare2 cp3_7(g[44],g[45],l[44],l[45],e[44],e[45],g[54],l[54],e[54]);
  compare2 cp3_8(g[46],g[47],l[46],l[47],e[46],e[47],g[55],l[55],e[55]);
  
  compare2 cp4_1(g[48],g[49],l[48],l[49],e[48],e[49],g[56],l[56],e[56]);
  compare2 cp4_2(g[50],g[51],l[50],l[51],e[50],e[51],g[57],l[57],e[57]);
  compare2 cp4_3(g[52],g[53],l[52],l[53],e[52],e[53],g[58],l[58],e[58]);
  compare2 cp4_4(g[54],g[55],l[54],l[55],e[54],e[55],g[59],l[59],e[59]);

  compare2 cp5_1(g[56],g[57],l[56],l[57],e[56],e[57],g[60],l[60],e[60]);
  compare2 cp5_2(g[58],g[59],l[58],l[59],e[58],e[59],g[61],l[61],e[61]);
  
  compare2 cp6(g[60],g[61],l[60],l[61],e[60],e[61],G_temp,L_temp,E_temp);
  
  assign G=~G_temp;
  assign L=~L_temp;
  assign E=~E_temp;

task compare1(
  input a,b,
  output g,l,e);
  reg w1;
begin
    w1= ~(a&b);
    g= ~(a&w1);
    l= ~(b&w1);
    e= ~(g&l);
end
endtask

task compare2(
  input a0,a1,b0,b1,c0,c1,
  output gg,ll,ee);
  reg p1,p2;
begin
   p1=c1|a0;
   p2=c1|b0;
   gg=p1&a1;
   ll=p2&b1;
   ee=c0|c1;
end
endtask

endmodule 

module testbench;
reg [31:0]A;
reg [31:0]B;
wire [61:0] g,l,e;
wire G,L,E;
main_fn  mf1(A,B,G,L,E,g,l,e);
initial
begin
$monitor(,$time," a0 = %b b0= %b A=%b, B=%b, G=%b, L=%b, E=%b,g=%b,l=%b,e=%b",A[0],B[0],A,B,G,L,E,g,l,e);
#0  A=32'b01010101010101010101010101010101;B=32'b10101010101010101010101010101010;
#100  A=32'b10101010101010101010101010101010;B=32'b01010101010101010101010101010101;
#200  A=32'b01010101010101010101010101010101;B=32'b01010101010101010101010101010101;
end
endmodule

and my test bench is showing the following results. Please help me in this

Code:

 0 a0 = 1 b0= 0 A=01010101010101010101010101010101, B=10101010101010101010101010101010, G=0, L=1, E=0,g=11111111111111111111111111111x101010101010101010101010101010x0,l=00000000000000000000000000000x010101010101010101010101010101x1,e=111111111111111111111111111111111111111111111111111111111111x1
#                   100 a0 = 0 b0= 1 A=10101010101010101010101010101010, B=01010101010101010101010101010101, G=1, L=0, E=0,g=00000000000000000000000000000x010101010101010101010101010101x1,l=11111111111111111111111111111x101010101010101010101010101010x0,e=111111111111111111111111111111111111111111111111111111111111x1
#                   300 a0 = 1 b0= 1 A=01010101010101010101010101010101, B=01010101010101010101010101010101, G=x, L=x, E=x,g=1x111x1111111x111111111111111x111111111111111111111111111111x1,l=1x111x1111111x111111111111111x111111111111111111111111111111x1,e=0x000x0000000x000000000000000x000000000000000000000000000000x0

Thanx in advance

qieda · Feb 28, 2011

Hi,

in line
compare1 cp1_2(A[l],B[l],g[1],l[1],e[1]);

you used an lowercase L for A and B bit selector and not a 1

regards

In my simulator I'm not able to enable tasks within a module. So for simulation I moved your tasks to modules

Code:

module compare1(
  input a,b,
  output g,l,e);
begin
  wire w1;
    assign w1= ~(a&b);
    assign g= ~(a&w1);
    assign l= ~(b&w1);
    assign e= ~(g&l);
end
endmodule

module compare2(
  input a0,a1,b0,b1,c0,c1,
  output gg,ll,ee);
begin
  wire p1,p2;
   assign p1=c1|a0;
   assign p2=c1|b0;
   assign gg=p1&a1;
   assign ll=p2&b1;
   assign ee=c0|c1;
end
endmodule


module main_fn (A,B,G,L,E,g,l,e);
  input [31:0] A;
  input [31:0] B; 
  output [61:0]g;
  output [61:0]l;
  output [61:0]e;
  wire G_temp,E_temp,L_temp;
  output G,L,E;

  compare1 cp1_1(A[0],B[0],g[0],l[0],e[0]);
  compare1 cp1_2(A[1],B[1],g[1],l[1],e[1]);
  compare1 cp1_3(A[2],B[2],g[2],l[2],e[2]);
  compare1 cp1_4(A[3],B[3],g[3],l[3],e[3]);
  compare1 cp1_5(A[4],B[4],g[4],l[4],e[4]);
  compare1 cp1_6(A[5],B[5],g[5],l[5],e[5]);
  compare1 cp1_7(A[6],B[6],g[6],l[6],e[6]);
  compare1 cp1_8(A[7],B[7],g[7],l[7],e[7]);
  compare1 cp1_9(A[8],B[8],g[8],l[8],e[8]);
  compare1 cp1_10(A[9],B[9],g[9],l[9],e[9]);
  compare1 cp1_11(A[10],B[10],g[10],l[10],e[10]);
  compare1 cp1_12(A[11],B[11],g[11],l[11],e[11]);
  compare1 cp1_13(A[12],B[12],g[12],l[12],e[12]);
  compare1 cp1_14(A[13],B[13],g[13],l[13],e[13]);
  compare1 cp1_15(A[14],B[14],g[14],l[14],e[14]);
  compare1 cp1_16(A[15],B[15],g[15],l[15],e[15]);
  compare1 cp1_17(A[16],B[16],g[16],l[16],e[16]);
  compare1 cp1_18(A[17],B[17],g[17],l[17],e[17]);
  compare1 cp1_19(A[18],B[18],g[18],l[18],e[18]);
  compare1 cp1_20(A[19],B[19],g[19],l[19],e[19]);
  compare1 cp1_21(A[20],B[20],g[20],l[20],e[20]);
  compare1 cp1_22(A[21],B[21],g[21],l[21],e[21]);
  compare1 cp1_23(A[22],B[22],g[22],l[22],e[22]);
  compare1 cp1_24(A[23],B[23],g[23],l[23],e[23]);
  compare1 cp1_25(A[24],B[24],g[24],l[24],e[24]);
  compare1 cp1_26(A[25],B[25],g[25],l[25],e[25]);
  compare1 cp1_27(A[26],B[26],g[26],l[26],e[26]);
  compare1 cp1_28(A[27],B[27],g[27],l[27],e[27]);
  compare1 cp1_29(A[28],B[28],g[28],l[28],e[28]);
  compare1 cp1_30(A[29],B[29],g[29],l[29],e[29]);
  compare1 cp1_31(A[30],B[30],g[30],l[30],e[30]);
  compare1 cp1_32(A[31],B[31],g[31],l[31],e[31]);

  compare2 cp2_1(g[0],g[1],l[0],l[1],e[0],e[1],g[32],l[32],e[32]);
  compare2 cp2_2(g[2],g[3],l[2],l[3],e[2],e[3],g[33],l[33],e[33]);
  compare2 cp2_3(g[4],g[5],l[4],l[5],e[4],e[5],g[34],l[34],e[34]);
  compare2 cp2_4(g[6],g[7],l[6],l[7],e[6],e[7],g[35],l[35],e[35]);
  compare2 cp2_5(g[8],g[9],l[8],l[9],e[8],e[9],g[36],l[36],e[36]);
  compare2 cp2_6(g[10],g[11],l[10],l[11],e[10],e[11],g[37],l[37],e[37]);
  compare2 cp2_7(g[12],g[13],l[12],l[13],e[12],e[13],g[38],l[38],e[38]);
  compare2 cp2_8(g[14],g[15],l[14],l[15],e[14],e[15],g[39],l[39],e[39]);
  compare2 cp2_9(g[16],g[17],l[16],l[17],e[16],e[17],g[40],l[40],e[40]);
  compare2 cp2_10(g[18],g[19],l[18],l[19],e[18],e[19],g[41],l[41],e[41]);
  compare2 cp2_11(g[20],g[21],l[20],l[21],e[20],e[21],g[42],l[42],e[42]);
  compare2 cp2_12(g[22],g[23],l[22],l[23],e[22],e[23],g[43],l[43],e[43]);
  compare2 cp2_13(g[24],g[25],l[24],l[25],e[24],e[25],g[44],l[44],e[44]);
  compare2 cp2_14(g[26],g[27],l[26],l[27],e[26],e[27],g[45],l[45],e[45]);
  compare2 cp2_15(g[28],g[29],l[28],l[29],e[28],e[29],g[46],l[46],e[46]);
  compare2 cp2_16(g[30],g[31],l[30],l[31],e[30],e[31],g[47],l[47],e[47]);
  
  compare2 cp3_1(g[32],g[33],l[32],l[33],e[32],e[33],g[48],l[48],e[48]);
  compare2 cp3_2(g[34],g[35],l[34],l[35],e[34],e[35],g[49],l[49],e[49]);
  compare2 cp3_3(g[36],g[37],l[36],l[37],e[36],e[37],g[50],l[50],e[50]);
  compare2 cp3_4(g[38],g[39],l[38],l[39],e[38],e[39],g[51],l[51],e[51]);
  compare2 cp3_5(g[40],g[41],l[40],l[41],e[40],e[41],g[52],l[52],e[52]);
  compare2 cp3_6(g[42],g[43],l[42],l[43],e[42],e[43],g[53],l[53],e[53]);
  compare2 cp3_7(g[44],g[45],l[44],l[45],e[44],e[45],g[54],l[54],e[54]);
  compare2 cp3_8(g[46],g[47],l[46],l[47],e[46],e[47],g[55],l[55],e[55]);
  
  compare2 cp4_1(g[48],g[49],l[48],l[49],e[48],e[49],g[56],l[56],e[56]);
  compare2 cp4_2(g[50],g[51],l[50],l[51],e[50],e[51],g[57],l[57],e[57]);
  compare2 cp4_3(g[52],g[53],l[52],l[53],e[52],e[53],g[58],l[58],e[58]);
  compare2 cp4_4(g[54],g[55],l[54],l[55],e[54],e[55],g[59],l[59],e[59]);

  compare2 cp5_1(g[56],g[57],l[56],l[57],e[56],e[57],g[60],l[60],e[60]);
  compare2 cp5_2(g[58],g[59],l[58],l[59],e[58],e[59],g[61],l[61],e[61]);
  
  compare2 cp6(g[60],g[61],l[60],l[61],e[60],e[61],G_temp,L_temp,E_temp);
  
  assign G=~G_temp;
  assign L=~L_temp;
  assign E=~E_temp;

endmodule 

module testbench;
reg [31:0]A;
reg [31:0]B;
wire [61:0] g,l,e;
wire G,L,E;
main_fn  mf1(A,B,G,L,E,g,l,e);
initial
begin
$monitor(,$time," a0 = %b b0= %b A=%b, B=%b, G=%b, L=%b, E=%b,g=%b,l=%b,e=%b",A[0],B[0],A,B,G,L,E,g,l,e);
#0  A=32'b01010101010101010101010101010101;B=32'b10101010101010101010101010101010;
#100  A=32'b10101010101010101010101010101010;B=32'b01010101010101010101010101010101;
#200  A=32'b01010101010101010101010101010101;B=32'b01010101010101010101010101010101;
end
endmodule // testbench

Adix149 · Feb 28, 2011

Hi thanx. It worked. My mistake

Why r tasks not compiling for you?? they are working fine for me.
Actually i have to synthesize this circuit using soc encounter. Will tasks work?? I read some where they do. But i thought using multiple modules would create a prob. so only used tasks. Help me in this. which is better for synthesizing Tasks or modules ??
Thanx for ur reply .

qieda · Feb 28, 2011

Hi,

I still think you need to have an always/initial block for calling your tasks.

Maybe for debugging you can look at my questions below.

regards

which simulator do you use? (I use Cadence enviroment)

did you compile at the beginning of your design a version of your design where you used modules for compare1 and compare2?
because it may be that there are still module definitions of compare1 and compare2 in your
previous compiled library
to avoid this can you remove your library and do a recompile?

can you check if you really use your tasks (e.g. by adding an error there)?

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Adix149

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qieda

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Adix149

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qieda

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