verilog to vhdl code convertion of pulse generator

[vimalpandey]

hi,
i am converting a verilog into vhdl, but i got struck at one instruction, please help me to understand what this instruction does. the instruction is as follows--
parameter DATA_WIDTH = 9
assign pulseOutSmall = {dataReg[0][DATA_WIDTH-1], // 1/4
dataReg[0][DATA_WIDTH-1],
dataReg[0][DATA_WIDTH-1],
dataReg[0][DATA_WIDTH-2:2]};
here pulseoutsmall is( output wire [DATA_WIDTH-1:0] pulseOutSmall) and dataReg is (reg [DATA_WIDTH-1:0] dataReg [0ULSE_LENGTH-1]

on running the code the value in the pulseoutsmall is 111000100 and value of dataReg[0] is 100010010

thanks in advance