Here is a simple example. It generates clk signal and should cause some warnings as described in initial section.
module width_check();
reg clk;
wire clock_wire;
assign clock_wire = clk;
specify
$width (negedge clock_wire, 10, 0);// clk should be at 0 at least 10 time units
$width (posedge clock_wire, 12, 0);// clk should be at 1 at least 12 time units
endspecify
initial
begin
#0 clk=0;
#(10+1) clk=1;//NO WARNING EXPECTED
#(12+1) clk=0;//NO WARNING EXPECTED
#3 clk=1;//3<10 WARNING EXPECTED
#5 clk=0;//5<12 WARNING EXPECTED
#20 $finish;
end
endmodule
And here is log fragment. It contains info about warnings got.
# KERNEL: C:\my_designs\temp\temp/src/temp.v(190): $width( negedge clock_wire:24 ns, :27 ns, 10 ns );
# KERNEL: Time: 27 ns Iteration: 1 Instance: /
# KERNEL: C:\my_designs\temp\temp/src/temp.v(191): $width( posedge clock_wire:27 ns, :32 ns, 12 ns );
# KERNEL: Time: 32 ns Iteration: 1 Instance: /