verilog timing check problem with $width

[thundermag]

Hello forum users,

I'm new in your forum and at first i want to say "hello"

I have a simulated testbench with verilog timing checks. The problem is, that no violation come on the $width check. The condition of $width is correct.
(threshold < time(opposite_event) - time(reference_event) < limit)

In one case, it is so, that the clk has a incorrect value of x, but the $width gives a correct violation !? Why come a violation when the signal is 'X'?

And the other problem is, when the clk is correct and the pulse width is in the violation range it comes no violation. Can explain me a user this behaviour?

thanks and
best regards
thundermag

 

[kornukhin]

Can you write your code example and waveform screenshot?

 

[thundermag]

here is the code:

reg pr_WIDTH_neg_C;
task p_WIDTH_neg_C;
input p_width;
reg [31:0] p_width;
begin
pr_WIDTH_neg_C <= 1;

set_C21 <= 1;

#(timeset_0);
C <= 0;
#(p_width - (Ic_r_BUX1 - Ic_f_BUX1));
C <= 1;
#(clk_period - p_width - timeset_0 + (Ic_r_BUX1 - Ic_f_BUX1));

set_C21 <= 0;

pr_WIDTH_neg_C <= 0;
end
endtask // p_WIDTH_neg_C

---------- Post added at 15:05 ---------- Previous post was at 15:03 ----------

here the picture:

**broken link removed**

i placed the cursors between the 2 edges. the value is 1281ps an there must came a violation

 

[kornukhin]

I simulate your example with the following width check

$width(posedge C, 10, 0);
every 0->X transition cause violation if X's width < 10 (0->X treats as posedge, that's why violation comes when the signal is 'X')

when I use
$width(negedge C, 10, 0);
every 1->0 transition cause violation if 0's width < 10

So what exactely width checks used in your simulation (posedge, negedge or both)?

 

[thundermag]

I use both checks in my simulation.
Ok also works the posedge violation correct.

And the negedge violation, I have ignored the the following
clk_rising = 472
clk_falling = 920
result: 0 < 472 - 920 < 1282
( -448 )

It is possible to check negedge and posedge in one simulation?
I have manual changed the times , so that the formula is correct, but no violation comes. So i think that the problem is an other.

 

[kornukhin]

Here is a simple example. It generates clk signal and should cause some warnings as described in initial section.

module width_check();
reg clk;
wire clock_wire;

assign clock_wire = clk;
specify
$width (negedge clock_wire, 10, 0);// clk should be at 0 at least 10 time units
$width (posedge clock_wire, 12, 0);// clk should be at 1 at least 12 time units
endspecify

initial
begin
#0 clk=0;
#(10+1) clk=1;//NO WARNING EXPECTED
#(12+1) clk=0;//NO WARNING EXPECTED
#3 clk=1;//3<10 WARNING EXPECTED
#5 clk=0;//5<12 WARNING EXPECTED
#20 $finish;
end

endmodule

And here is log fragment. It contains info about warnings got.

# KERNEL: C:\my_designs\temp\temp/src/temp.v(190): $width( negedge clock_wire:24 ns, :27 ns, 10 ns );
# KERNEL: Time: 27 ns Iteration: 1 Instance: /
# KERNEL: C:\my_designs\temp\temp/src/temp.v(191): $width( posedge clock_wire:27 ns, :32 ns, 12 ns );
# KERNEL: Time: 32 ns Iteration: 1 Instance: /