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verilog, the wait statement

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Newbie level 3
Jun 2, 2015
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How to describe in Verilog delay first byte before the arrival emacclienttxack?

Screenshot - 02.06.2015 - 14:04:36.jpg

Thanks very much!

with flip-flops and the the clock used to drive the signals shown? i.e. wait (delay) isn't synthesizable.

Based on your question I think you are attempting to write software (the wrong way) instead of hardware (the right way).

what kind of hardware I should to use ?

what kind of hardware I should to use ?

Well you're in a programmable logic (e.g. CPLD, FPGA, etc) area of the forum, so I'd say you would use an FPGA as your hardware platform?

If you meant which Hardware Description Language (HDL) to use, then either Verilog or VHDL will work. Just understand that you are writing hardware descriptions, not software code, so you won't be "programming" you'll be coding a behavioral description of a hardware design.

If you haven't already you should read a book on Verilog/VHDL and online tutorials like the one at asic-world.

I'm using Xilinx WebPack with spartan6 XC6SLX100. I took tri mode eth mac v4.5 module. I want to write state-machines on Verilog wich would describe the picture above. I mean, that I want to send ethernet frame, but the first byte have to sending continuously and then when emacclienttxack will arrive I send other piece of frame. But, I can't do it, because I'm bad programmist on verilog.

I'm realy sorry about my english))

But, I can't do it, because I'm bad programmist on verilog.
You can't do it because you are trying to "program" in Verilog.

Draw a schematic of the digital logic design that does what you want. If you don't know how to design the digital logic then you need to learn digital logic design first, because you need to know what logic you want before writing a description of it in Verilog.

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