Verilog Testbench to monitor signal relationship

[aspirinnnnn]

I am currently working on a CMOS Image Sensor controller. this controller has to give a huge control signals to the ADC and Pixel array. those signals has its fixed relationship like:
a is pull up high for 10 clock,then pull down for 15 clock and .....
b is pull up high one clock behind the a ,and then stay high for xxx clock
c is ........

how do i achieve auto automatically test in testbench, thanks for any helps

 

[dave_59]

This is something SystemVerilog Assertions (SVA) could help with very easily. See https://verificationacademy.com/courses/assertion-based-verification as well as many other online resources for SystemVerilog assertions.

 

[aspirinnnnn]

This is something SystemVerilog Assertions (SVA) could help with very easily. See https://verificationacademy.com/courses/assertion-based-verification as well as many other online resources for SystemVerilog assertions.

Thank You Very Much ,It Helps me a lot