Verilog testbench for VHDL RTL

snehaganesh · Aug 28, 2007

Can I write Verilog Testbenches to verify VHDL entities... Are there any constraints in doing so?

omara007 · Aug 28, 2007

As testbench is simply considered a top level for the Design Under Test, then you can use a Verilog testbench to test a VHDL component. This is done by instantiating the VHDL component inside the Verilog testbench the same way you instantiate a verilog block. Just make sure that you environment supports mixed-language designs.

rajsrikanth · Aug 28, 2007

yes u can do that, becoz we actually take the instantiation of the class that is given in testbench. it does not matter when u are instantiating any entity or module.

ameed · Aug 30, 2007

hi,

yes you can do that.

thanx.....

gck · Sep 4, 2007

Ya we can do that.
For that instantiation of VHDL model has to be done in verilog test bench.
You need to read the documentation of the perticular simulation tool before simulation.

Modelsim u can go through the chapter called Mixed mode simulation

Verilog testbench for VHDL RTL

snehaganesh

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gck

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Verilog testbench for VHDL RTL

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