Verilog synthesizable construct for a signal which changes

[sun_ray]

I have a signal with 10 bit width. I want to assign do an operation while this 10 bit signal changes. Can anybody please let me know the synthesizable construct to indicate that whenver this signal 9:0 width changes , an operation can be done?

Let the signal name be is high_volt[9:0]. Whenever high_volt changes I need to do an addition of two other signals named low_volt and medium_volt.

Will @high_volt work? If you please write the complete construct to add low_volt and medium_volt.

 

[FvM]

The only synthesizable way is synchronous logic comparing a previous registered with the actual input value.

Level sensitive events like @high_volt work are only relevant for simulation and ignored in synthesis.

 

[sun_ray]

The only synthesizable way is synchronous logic comparing a previous registered with the actual input value.

Level sensitive events like @high_volt work are only relevant for simulation and ignored in synthesis.

Can you please provide the complete construct in verilog of using @high_volt even if it only works for simulation. Will it need an always block? Can you please write the code portion for it in verilog?

Regards