Verilog simulation error: instantiation of alu_operation failed

[sriramsv]

hi,

I'm trying to simulate a simple verilog program(alu operation).i can compile the module n test bench. but when i wanted to simulate it, i'm getting an error

Loading work.test_bench_alu_operation
# ** Error: (vsim-3033) C:/Modeltech_xe_starter/my examples/test_bench_alu_operation.v(6): Instantiation of 'alu_operaion' failed. The design unit was not found.
# Region: /test_bench_alu_operation
# Searched libraries:
# work
# Error loading design

alu_operation is in library "work". Can anyone tell me what will be the problem.

tanx

 

[iamczx]

verilog and alu

Error: (vsim-3033) C:/Modeltech_xe_starter/my examples/test_bench_alu_operation.v(6): Instantiation of 'alu_operaion' failed. The design unit was not found.


check your code . May you write wrong module name.

 

[omara007]

error: (vsim-3033)

check ur library map in modelsim .. maybe ur mapping ur library to some other place