Verilog NEXYS2 board constraints help

[vveerendra]

Hello,
I want to dump my verilog code to the nexys2 board

can anyone please help me to fix the problem

here m and n are acting like enble pins to the d-flipflops both the pins are taking inputs from the same source([5:0]qx)
when I try to generate the programme bit file it gave me the following error

NET "m" CLOCK_DEDICATED_ROUTE = FALSE


module(....);


always @(qx)
case({m,n})
2'b01 :begin y=y; x=qx; end
2'b10 :begin y=qx; x=x; end
2'b11 :begin y=qx; x=qx; end
default :begin y=y; x=x; end
endcase


endmodule

this is my constraints file
#switches
NET "qx[0]" LOC = "K18";
NET "qx[1]" LOC = "K17";
NET "qx[2]" LOC = "L14";
NET "qx[3]" LOC = "L13";
NET "qx[4]" LOC = "N17";
NET "qx[5]" LOC = "R17";
NET "CLK" LOC ="B8";
NET "n" LOC ="G18";
NET "m" LOC ="H18";


#DISP
NET "A[0]" LOC = "H14";
NET "A[1]" LOC = "J17";
NET "A[2]" LOC = "G14";
NET "A[3]" LOC = "D16";
NET "A[4]" LOC = "D17";
NET "A[5]" LOC = "F18";
NET "A[6]" LOC = "L18";
NET "ano[0]" LOC = "F17";
NET "ano[1]" LOC = "H17";
NET "ano[2]" LOC = "C18";
NET "ano[3]" LOC = "F15";

please help me thank you!!