achundur
Junior Member level 1
Hi all:
I have my design in VHDL and after sythesis using synopsys Design compiler , I generated a vhdl netlist and a verilog netlist. The post synthesis simulation of gate level netlist in VHDL is working fine but verilog netlist simulation is giving all "zeros in output" . Anyone has any clue why this could happen?
I used the following command for writing verilog netlist and there are no warnings shown by Designcompiler while writing verilog netlist
write -hierarchy push_unit -format verilog -output push_unit_syn.v
Thanks
I have my design in VHDL and after sythesis using synopsys Design compiler , I generated a vhdl netlist and a verilog netlist. The post synthesis simulation of gate level netlist in VHDL is working fine but verilog netlist simulation is giving all "zeros in output" . Anyone has any clue why this could happen?
I used the following command for writing verilog netlist and there are no warnings shown by Designcompiler while writing verilog netlist
write -hierarchy push_unit -format verilog -output push_unit_syn.v
Thanks
