module add_8bit ( output wire co,
output wire [7:0] r,
input wire ci,
input wire [7:0] x,
input wire [7:0] y );
add_1bit t0 ( r[0], ci, x[0], y[0], ci ) ;
add_1bit t1 ( r[1], ci, x[1], y[1], ci ) ;
add_1bit t2 ( r[2], ci, x[2], y[2], ci ) ;
add_1bit t3 ( r[3], ci, x[3], y[3], ci ) ;
add_1bit t4 ( r[4], ci, x[4], y[4], ci ) ;
add_1bit t5 ( r[5], ci, x[5], y[5], ci ) ;
add_1bit t6 ( r[6], ci, x[6], y[6], ci ) ;
add_1bit t7 ( r[7], co, x[7], y[7], ci ) ;
endmodule
//adds 2 bits together
module add_1bit ( output wire r,
output wire co,
input wire x,
input wire y,
input wire ci );
//wires to carry results of operations
wire w0, w1, w2 ;
//XOR x and y and put on wire w0
xor t0 ( w0, x, y ) ;
//AND x and y and put on wire w1
and t1 ( w1, x, y ) ;
//XOR w0 and ci to get result
xor t2 ( r, w0, ci ) ;
//AND w0 and ci
and t3 ( w2, w0, ci ) ;
//OR w1 and w2 to get carry out
or t4 ( co, w1, w2 ) ;
endmodule