Verilog: Need help with 8bit adder!

[boblettoj99]

Hi, i have a weird problem with my coursework, basically we have to write an 8 bit adder using only logic gates. This is my first time using verilog and i'm sure you'll agree its very confusing coming from C programming to this!

Anyway, these two modules are what i have come up with, the 1bit adder works perfectly however when i test the 8bit one it doesn't work properly, as far as i can tell the carry-in is not being assigned properly and stays at 0 throughout the whole calculation. Can anyone tell me why this is?
Thanks, Ed.

module add_8bit ( output wire      co,
                  output wire [7:0] r,
                  
                  input wire       ci,
                  input wire [7:0]  x,
                  input wire [7:0]  y );
                  
  add_1bit t0 ( r[0], ci, x[0], y[0], ci ) ;
  add_1bit t1 ( r[1], ci, x[1], y[1], ci ) ;
  add_1bit t2 ( r[2], ci, x[2], y[2], ci ) ;
  add_1bit t3 ( r[3], ci, x[3], y[3], ci ) ;
  add_1bit t4 ( r[4], ci, x[4], y[4], ci ) ;
  add_1bit t5 ( r[5], ci, x[5], y[5], ci ) ;
  add_1bit t6 ( r[6], ci, x[6], y[6], ci ) ;
  add_1bit t7 ( r[7], co, x[7], y[7], ci ) ;
endmodule

//adds 2 bits together
module add_1bit ( output wire r,
                  output wire co,
                  input wire x,
                  input wire y,
                  input wire ci );

  //wires to carry results of operations                
  wire w0, w1, w2 ;

  //XOR x and y and put on wire w0
  xor t0 ( w0, x, y ) ;
  //AND x and y and put on wire w1
  and t1 ( w1, x, y ) ;

  //XOR w0 and ci to get result
  xor t2 ( r, w0, ci ) ;

  //AND w0 and ci
  and t3 ( w2, w0, ci ) ;

  //OR w1 and w2 to get carry out
  or t4 ( co, w1, w2 ) ;

endmodule

 

[bapodradhairyab]

dear friend
when you define 8 bit adder you need to define carries of intermediate stages as wire ...

you cant put same ci as input to all 8 bit adder..
define wire c1,c2,c3,c4,c5,c6,c7 and replace module instance like this....

Added after 1 minutes:

add_1bit t0 ( r[0], c1, x[0], y[0], ci ) ;
add_1bit t1 ( r[1], c2, x[1], y[1], c1 ) ;
add_1bit t2 ( r[2], c3, x[2], y[2], c2 ) ;
add_1bit t3 ( r[3], c4, x[3], y[3], c3 ) ;
add_1bit t4 ( r[4], c5, x[4], y[4], c4 ) ;
add_1bit t5 ( r[5], c6, x[5], y[5], c5 ) ;
add_1bit t6 ( r[6], c7, x[6], y[6], c6 ) ;
add_1bit t7 ( r[7], co, x[7], y[7], c7 ) ;

Added after 2 minutes:

hope it had clear you doubt for more understanding read digital and about adders.... and see this image...

https://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/20-arithmetic/10-adders/ripple.gif

 

[boblettoj99]

Ahh thankyou very much that works great, however i have a different problem now. I have made a subtractor which takes in signed integers x and y and attempts to subtract y from x. I am doing this by converting y into 2's complement and then adding it to x with the 8 bit adder like this:

module sub_8bit ( output wire [7:0]  r,
                       output wire       co,
                       
                       input wire  [7:0] ci,
                       input wire  [7:0]  x,
                       input wire  [7:0]  y ) ;
  wire [7:0] w0, w1, w2;
        
  //NOT y and add 1 (complement)
  not t0 ( w0[0], y[0] ) ;
  not t1 ( w0[1], y[1] ) ;
  not t2 ( w0[2], y[2] ) ;
  not t3 ( w0[3], y[3] ) ;
  not t4 ( w0[4], y[4] ) ;
  not t5 ( w0[5], y[5] ) ;
  not t6 ( w0[6], y[6] ) ;
  not t7 ( w0[7], y[7] ) ;
  add_8bit t8 ( w2, w1, 1'b0, w0, 8'b0000_0001 ) ;
  
  //add x and complemented y
  add_8bit t9 ( co, r, 1'b0, x, w1 ) ;
  
endmodule

this calls my updated add_8bit module:

module add_8bit ( output wire      co,
                  output wire [7:0] r,
                  
                  input wire [7:0] ci,
                  input wire [7:0]  x,
                  input wire [7:0]  y );
                  
  add_1bit t0 ( r[0], ci[0], x[0], y[0], 1'b0) ;
  add_1bit t1 ( r[1], ci[1], x[1], y[1], ci[0] ) ;
  add_1bit t2 ( r[2], ci[2], x[2], y[2], ci[1] ) ;
  add_1bit t3 ( r[3], ci[3], x[3], y[3], ci[2] ) ;
  add_1bit t4 ( r[4], ci[4], x[4], y[4], ci[3] ) ;
  add_1bit t5 ( r[5], ci[5], x[5], y[5], ci[4] ) ;
  add_1bit t6 ( r[6], ci[6], x[6], y[6], ci[5] ) ;
  add_1bit t7 ( r[7], co, x[7], y[7], ci[6] ) ;
endmodule

When i simulate the add_8bit function directly it gives me the correct output every time however when i call it from the sub_8bit module it gives me unknown Xs for some of my carry in values and the result. What could be causing it? There's nothing wrong with the adder as far as i can tell!
thanks

 

[mux_master]

Your problem is most likely resulting from an input going undefined. An undefined value will produce the 'X' in verilog simulation. Once this gets into your logic, it will be propagated. The way to solve the problem is to track down the source of the 'X' generation. Looking at your code quickly, I see that the ci of the t8 add_8bit goes undefined. Then I noticed that you have a 1 bit signal connected to the 8 bit input. This leaves 7 bits undefined. This would be a good place to start looking.