Verilog for loop error.

[Rohit Ranjan]

I am encountering this error. I think I just need someones second eye on it.
Tool: Modelsim
Error:
near "+": syntax error, unexpected '+'

Here is the section of code

initial
begin // Populate the memory.
firstvalue = 10;
for (iter=0;iter<=20;iter + 1)
begin
mem_array[iter]= firstvalue;
firstvalue = firstvalue +10;
#10;
end
end

Please help.Thankd in Advance

 

[alexhugo]

It should be iter=iter+1

 

[Rohit Ranjan]

Thanks alexhugo,

Now I am getting an error that say
'iter' is an invalid type in Generate loop. Must be a genvar