Verilog doubts about sensitivity list code

[vikas_lakhanpal27]

Verilog doubts

In two years of my exp in VLSI industry first time I saw a code in verilog in which senstivity list looks like

always @(posedge clk or negedge rst or negedge pwrfail)

I am trying to see how will Dc synthsize it. In between wat u ppl think is it good way to write code? And any idea how will DC synthsize it?

Acc to me we should check only one negedge or posedge + another signals in the senstivity list.

please give ur valucable comments!

regards,
Vikas

 

[pramodm]

Verilog doubts

the sensitivity list is acceptable

 

[vikas_lakhanpal27]

Verilog doubts

Hi parmod,
thanks for the reply.I agreed that it is acceptable but is it a good design practice?

 

[FvM]

Re: Verilog doubts

You should consider that a sensitivity list with a clock usually infers a group of flip-flops with synchronous clock and asynchronous reset. The expression only appearing in the sensitivity list is the clock, the others make up the reset. If the reset condition in your example would be (~reset || ~pwrfail), it could act as one. A negedge with positive reset condition would cause an error with most Verilog compilers, probably this is also the case with impossible signal combinations.

 

[prashanthknl]

Re: Verilog doubts

I think you should rethink about the DFT rules even if its synthesized with a negative sensitive reset and a positive edge triggred clock

 

[sumit_techkgp]

Verilog doubts

Hi Vikas, there will be an or gate on the next two sensitive list member. This should not pose any DFT issue as the reset signal entering the flop will be muxed, so i dont see any such issue. But one thing i want to pint out, U should not write that. Any bug or issue is difficult to analyze.