vlsi_freak
Full Member level 2
Hi,
My verilog code is shown below,
I am unable to make out the waveform, what actually this statement does.
Can anyone share your thoughts.
Regards,
freak
My verilog code is shown below,
Code:
module tq ( input a, output reg b);
always (*)
b = #5 a;
endmodule
I am unable to make out the waveform, what actually this statement does.
Can anyone share your thoughts.
Regards,
freak