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# Verilog delay modelling

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#### vlsi_freak

##### Full Member level 2
Hi,

My verilog code is shown below,

Code:
module tq ( input a, output reg b);

always (*)

b = #5 a;

endmodule

I am unable to make out the waveform, what actually this statement does.

Regards,
freak

Hi,

My verilog code is shown below,

Code:
module tq ( input a, output reg b);

always (*)

b = #5 a;

endmodule

I am unable to make out the waveform, what actually this statement does.

Regards,
freak

Above code has syntax errors and it won't compile
If you make some slight changes
It should work ...
Code:
module tq ( input a, output reg b);

always

b = #5 a;

endmodule

Output will be a delayed form of a ...

Another way to make it work

Code:
 module tq ( input a, output reg b);

always @(*)

b = #5 a;

endmodule

here are some good material on verilog delay modeling

1.h**p://www.see.ed.ac.uk/~gerard/Teach/Verilog/mjta/Gateway/html/delays.html
2.h**p://inst.eecs.berkeley.edu/~cs152/fa04/handouts/CummingsHDLCON1999_BehavioralDelays_Rev1_1.pdf

Last edited:

I have a question.

I am trying to understanding this statement. Its a part of specifying delays of standard cells.

********
specify
(A1 => ZN) = (x1, y1);
(A2 => ZN) = (x2, y2);
endspecify

************

I understand thats rising and falling delays respectively.

But does this mean that x1 is rising delay of A1 and y1 is falling delay of A1 or x1 is rising delay of ZN and y1 is falling delay of ZN, while input is A1?

I am confsed!

Found the answer of the question posted above.

x1 rising delay of ZN and y1 is falling delay of ZN while input is A1.

Thanks.

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