Verilog Compilation problem in module instantiation

[rmmy]

I am trying to compile this verilog code. I am getting this error message. I am not able to understnd this error message.


Error Message:
# ** Error: /nfs/iind/disks/egl_fe_0001/people/mrangapu/spine/clock/x.v(21): near "endmodule": syntax error, unexpected "endmodule", expecting ')'. 21st line is the last line of instantiation.

Code:
module x (
input xin,
output [18:10] ckuclksysintgdxx
);

ckuclksysinthzsliced ckuclksysinthzsliced2l (
.hopin (xin),
.\ckuclksysintgd[1] (\ckuclksysintgdxx[10]),
.\ckuclksysintgd[2] (\ckuclksysintgdxx[11]),
.\ckuclksysintgd[3] (\ckuclksysintgdxx[12]),
.\ckuclksysintgd[4] (\ckuclksysintgdxx[13]),
.\ckuclksysintgd[5] (\ckuclksysintgdxx[14]),
.\ckuclksysintgd[6] (\ckuclksysintgdxx[15]),
.\ckuclksysintgd[7] (\ckuclksysintgdxx[16]),
.\ckuclksysintgd[8] (\ckuclksysintgdxx[17]),
.\ckuclksysintgd[9] (\ckuclksysintgdxx[18])
); --> getting error for this line

endmodule

module ckuclksysinthzsliced (

input hopin,
inout [9:1] ckuclksysintgdr

);

wire pguclks16, pguclks17l, pguclks17m, pguclks17r;

egl_ckdistinv ckdistinv_tbr1(
.clkin(hopin),
.clkout(pguclks16)
);
x
egl_ckdistinv ckdistinv_tbr2(
.clkin(pguclks16),
.clkout(pguclks17m)
);

egl_ckdistinv ckdistinv_tbr3(
.clkin(pguclks16),
.clkout(pguclks17l)
);

egl_ckdistinv ckdistinv_tbr4(
.clkin(pguclks16),
.clkout(pguclks17r)
);


genvar jump_l;
generate
for (jump_l=1; jump_l < 4; jump_l=jump_l+1) begin:jumperin3
egl_ckdistinv ckdistinv_tbr_jump_l(
.clkin(pguclks17l),
.clkout(\ckuclksysintgdr[jump_l] )
);
end
endgenerate

genvar jump_r;
generate
for (jump_r=7; jump_r < 10; jump_r= jump_r+1) begin:jumperin4
egl_ckdistinv ckdistinv_tbr_jump_r(
.clkin(pguclks17r),
.clkout(\ckuclksysintgdr[jump_r] )
);
end
endgenerate

genvar jump_m;
generate
for (jump_m=4; jump_m < 7; jump_m=jump_m+1) begin:jumperin5
egl_ckdistinv ckdistinv_tbr_jump_m(
.clkin(pguclks17m),
.clkout(\ckuclksysintgdr[jump_m] )
);
end
endgenerate


// The following is 0in assertion code
//
`ifdef ZI_INLINED_CHX
`include "ckuclksysinthzsliced.zi_chx.inc"
`else
`ifdef ZI_INLINED_CHX_ckuclksysinthzsliced
`include "ckuclksysinthzsliced.zi_chx.inc"
`endif
`endif


endmodule // ckuclksysinthzsliced

 

[soloktanjung]

Hi,

I looked at glance on your code. I found out that there is mismatch signal's name used in the instantiation.

\ckuclksysintgd[1] in module x

with

ckuclksysintgdr in module ckuclksysinthzsliced


Correct it and recompile the code.

Thanks.

 

[pete_lu]

naming conflection: "ckuclksysintgd" in module x, "ckuclksysintgdr" in instantiated module ckuclksysinthzsliced.